Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18103
Pao-Po Hou, R. Owens, M. J. Irwin
The authors present DECOMPOSER, a high-level synthesis tool for automating the design of systolic systems. DECOMPOSER takes as inputs a hierarchical description of the computation to be performed and some hint as to how it is to be performed. The computation description is in the form of a parameterized DAG (directed acyclic graph) so that different problem sizes can be handled. The hit is in the form of marking information for that DAG. DECOMPOSER produces a detailed report on the hardware requirements for the specified computation. In particular, the structure of each computation node, how the computation nodes are connected, and the input and output sequences are given. The information is passed to other tools in the tool set so that ultimately a layout description file in suitable format (e.g. CIF) can be generated for the architecture performing the computation derived by DECOMPOSER.<>
{"title":"A high level synthesis tool for systolic designs","authors":"Pao-Po Hou, R. Owens, M. J. Irwin","doi":"10.1109/ARRAYS.1988.18103","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18103","url":null,"abstract":"The authors present DECOMPOSER, a high-level synthesis tool for automating the design of systolic systems. DECOMPOSER takes as inputs a hierarchical description of the computation to be performed and some hint as to how it is to be performed. The computation description is in the form of a parameterized DAG (directed acyclic graph) so that different problem sizes can be handled. The hit is in the form of marking information for that DAG. DECOMPOSER produces a detailed report on the hardware requirements for the specified computation. In particular, the structure of each computation node, how the computation nodes are connected, and the input and output sequences are given. The information is passed to other tools in the tool set so that ultimately a layout description file in suitable format (e.g. CIF) can be generated for the architecture performing the computation derived by DECOMPOSER.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"28 2 Suppl 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123436766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18052
N. Bourbakis, F. Barlos
The performance of the various parts of the HERMES multiprocessor vision system is evaluated. HERMES is an autonomous, hierarchical, heterogenic vision processing system, consisting of N/sup 2//4/sup i/, 0>
{"title":"Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks","authors":"N. Bourbakis, F. Barlos","doi":"10.1109/ARRAYS.1988.18052","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18052","url":null,"abstract":"The performance of the various parts of the HERMES multiprocessor vision system is evaluated. HERMES is an autonomous, hierarchical, heterogenic vision processing system, consisting of N/sup 2//4/sup i/, 0<or=i<or=log/sub 2/N, processor nodes, where N*N is the size of a picture and i is a resolution parameter. HERMES receives the picture information directly from the environment, using photoarrays, and processes them in a parallel hierarchical manner. One major characteristic of this system is that it does not need a host computer. A variety of simple processing algorithms is described and their execution time is calculated, providing a basis for the performance evaluation.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123682087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18100
S. P. Popli, M. Bayoumi
The fault-tolerance scheme consists of two phases: testing and locating faults (fault diagnosis), and reconfiguration. The first phase uses an online error-detection technique that achieves a compromise between the space and time redundancy approaches. This technique reduces the rollback time considerably and is capable of detecting permanent as well as transient faults. Reconfiguration consists of mapping the function of the faulty processor element onto an adjacent nonfaulty neighbor, which is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. A reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.<>
{"title":"A reconfigurable VLSI array for reliability and yield enhancement","authors":"S. P. Popli, M. Bayoumi","doi":"10.1109/ARRAYS.1988.18100","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18100","url":null,"abstract":"The fault-tolerance scheme consists of two phases: testing and locating faults (fault diagnosis), and reconfiguration. The first phase uses an online error-detection technique that achieves a compromise between the space and time redundancy approaches. This technique reduces the rollback time considerably and is capable of detecting permanent as well as transient faults. Reconfiguration consists of mapping the function of the faulty processor element onto an adjacent nonfaulty neighbor, which is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. A reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133735820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18078
E. Omtzigt
Research on mapping regular iterative algorithms onto dedicated systolic/wavefront arrays has been directed toward defining a unified framework in which to represent and formally synthesize and analyze systolic array designs so that the design can be supported, or even automated, by a computer-aided-design system. The author presents such a design system, SYSTARS, which supports the design trajectory from algorithm to partitioned systolic array with a very flexible, comprehensive, and animative 3-D graphics environment, and extends the partitioning of full-size arrays with a fully automatic adaptive cluster algorithm and corresponding control extraction. SYSTARS effectively uses geometric representations of the algorithm, full-size systolic array, and partitioned systolic array, which makes is appropriate for the development of better systolic algorithms, better mappings, and better partitioning strategies.<>
{"title":"SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays","authors":"E. Omtzigt","doi":"10.1109/ARRAYS.1988.18078","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18078","url":null,"abstract":"Research on mapping regular iterative algorithms onto dedicated systolic/wavefront arrays has been directed toward defining a unified framework in which to represent and formally synthesize and analyze systolic array designs so that the design can be supported, or even automated, by a computer-aided-design system. The author presents such a design system, SYSTARS, which supports the design trajectory from algorithm to partitioned systolic array with a very flexible, comprehensive, and animative 3-D graphics environment, and extends the partitioning of full-size arrays with a fully automatic adaptive cluster algorithm and corresponding control extraction. SYSTARS effectively uses geometric representations of the algorithm, full-size systolic array, and partitioned systolic array, which makes is appropriate for the development of better systolic algorithms, better mappings, and better partitioning strategies.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116393108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18068
S. Jou, C. Jen, W. Shen
The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-scheduling and node-assignment procedures to this tagged DG, the interfacing communication problem of a systolic array system can be solved and the optimal latency can be easily obtained. Using this method, an optimal linear-state solver has been designed.<>
{"title":"The design of a systolic array system for linear state equations","authors":"S. Jou, C. Jen, W. Shen","doi":"10.1109/ARRAYS.1988.18068","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18068","url":null,"abstract":"The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-scheduling and node-assignment procedures to this tagged DG, the interfacing communication problem of a systolic array system can be solved and the optimal latency can be easily obtained. Using this method, an optimal linear-state solver has been designed.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116605419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18057
S. King
The key aspects of the modeling, algorithm, and architecture for artificial neural nets (ANNs) are reviewed. A programmable systolic array meant for a variety of connectivity patterns for ANNs is proposed. Considered in the design are both the search and learning phases of a class of ANNs. A system-theoretic approach is adopted to elucidate modeling issues for ANNs. On the basis the issues of expressibility and discrimination, fault tolerance and generalization, size of hidden units/layers, interconnectivity patterns, and circuit model for analog ANN implementations are addressed.<>
{"title":"Parallel architectures for artificial neural nets","authors":"S. King","doi":"10.1109/ARRAYS.1988.18057","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18057","url":null,"abstract":"The key aspects of the modeling, algorithm, and architecture for artificial neural nets (ANNs) are reviewed. A programmable systolic array meant for a variety of connectivity patterns for ANNs is proposed. Considered in the design are both the search and learning phases of a class of ANNs. A system-theoretic approach is adopted to elucidate modeling issues for ANNs. On the basis the issues of expressibility and discrimination, fault tolerance and generalization, size of hidden units/layers, interconnectivity patterns, and circuit model for analog ANN implementations are addressed.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121906376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18092
R. Philhower, J. F. Mcdonald
The impact of interprocessor communication complexity in systolic arrays is considered. These issues are explored in the context of the design for a compact processor capable of processing 1000 billion systolic operations per second. The goal is to realize the processor in a compact wafer scale hybrid package (WSHP) using sixteen 8-in-diameter wiring substrates with roughly 70 systolic processor cells mounted in piggyback fashion on top of them. It is shown that except in the simplest cases the interprocessor wiring substrate may require some form of repair strategy to be fabricatable. In any case, some means for testing the substrate wiring will be required. The use of a focused ion beam and a means of accomplishing test and repair for a passive wiring substrate is briefly examined.<>
{"title":"Interconnection complexity study for a piggy back WSHP GaAs systolic processor","authors":"R. Philhower, J. F. Mcdonald","doi":"10.1109/ARRAYS.1988.18092","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18092","url":null,"abstract":"The impact of interprocessor communication complexity in systolic arrays is considered. These issues are explored in the context of the design for a compact processor capable of processing 1000 billion systolic operations per second. The goal is to realize the processor in a compact wafer scale hybrid package (WSHP) using sixteen 8-in-diameter wiring substrates with roughly 70 systolic processor cells mounted in piggyback fashion on top of them. It is shown that except in the simplest cases the interprocessor wiring substrate may require some form of repair strategy to be fabricatable. In any case, some means for testing the substrate wiring will be required. The use of a focused ion beam and a means of accomplishing test and repair for a passive wiring substrate is briefly examined.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121974411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18046
G. Panneerselvam, G. Jullien, W. Miller
Two- and three-dimensional systolic architectures are proposed for the hash table data structure (hashing). The parallel systolic hashing architecture provides the facility for implementing the hash operations of Insert, Delete, and Member in a constant time complexity. The importance and advantages of extending sequential hashing to a parallelized form are discussed. An implementation is presented of a sorting problem of N numbers in an O(L) time complexity, where L is constant, using a three-dimensional parallelized systolic hashing process. This is compared to a sequential hashing process, which requires O(N) time complexity.<>
{"title":"New architectures for systolic hashing","authors":"G. Panneerselvam, G. Jullien, W. Miller","doi":"10.1109/ARRAYS.1988.18046","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18046","url":null,"abstract":"Two- and three-dimensional systolic architectures are proposed for the hash table data structure (hashing). The parallel systolic hashing architecture provides the facility for implementing the hash operations of Insert, Delete, and Member in a constant time complexity. The importance and advantages of extending sequential hashing to a parallelized form are discussed. An implementation is presented of a sorting problem of N numbers in an O(L) time complexity, where L is constant, using a three-dimensional parallelized systolic hashing process. This is compared to a sequential hashing process, which requires O(N) time complexity.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"1973 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130069445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18054
F. Ling
Three systolic arrays suitable for implementation of order-recursive least-squares (ORLS) adaptive algorithms are considered. It is shown that they can be constructed using two types of elementary cells. A classification of systolic implementations of the ORLS adaptive algorithms is given by exploiting the possible variations of the elementary cells. The investigation of the array structures and variations of the elementary cells leads to a systematic approach to designing reconfigurable systolic arrays for implementation of ORLS algorithms. As an application of this approach, a novel least-squares (LS) lattice algorithm based on Givens rotations is derived.<>
{"title":"Systolic arrays for implementation of order-recursive least-squares adaptive filtering algorithms","authors":"F. Ling","doi":"10.1109/ARRAYS.1988.18054","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18054","url":null,"abstract":"Three systolic arrays suitable for implementation of order-recursive least-squares (ORLS) adaptive algorithms are considered. It is shown that they can be constructed using two types of elementary cells. A classification of systolic implementations of the ORLS adaptive algorithms is given by exploiting the possible variations of the elementary cells. The investigation of the array structures and variations of the elementary cells leads to a systematic approach to designing reconfigurable systolic arrays for implementation of ORLS algorithms. As an application of this approach, a novel least-squares (LS) lattice algorithm based on Givens rotations is derived.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122530016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-05-25DOI: 10.1109/ARRAYS.1988.18069
C. Ko, O. Wing
A mapping strategy for automatic design of systolic arrays is presented. Algorithms are specified in terms of data dependency and identity, and implementations are specified in terms of data propagation and sequence behavior. By establishing a relation between data propagation and sequence, an optimal mapping strategy is formulated as a problem of finding an integer solution of a set of linear equations. This approach provides a uniform framework to design a variety of systolic arrays. An automatic design program and some design examples are presented.<>
{"title":"Mapping strategy for automatic design of systolic arrays","authors":"C. Ko, O. Wing","doi":"10.1109/ARRAYS.1988.18069","DOIUrl":"https://doi.org/10.1109/ARRAYS.1988.18069","url":null,"abstract":"A mapping strategy for automatic design of systolic arrays is presented. Algorithms are specified in terms of data dependency and identity, and implementations are specified in terms of data propagation and sequence behavior. By establishing a relation between data propagation and sequence, an optimal mapping strategy is formulated as a problem of finding an integer solution of a set of linear equations. This approach provides a uniform framework to design a variety of systolic arrays. An automatic design program and some design examples are presented.<<ETX>>","PeriodicalId":339807,"journal":{"name":"[1988] Proceedings. International Conference on Systolic Arrays","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124001902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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