Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329120
A. Klausner, B. Rinner, A. Tengg
I-SENSE demonstrates the potential of combining the scientific research areas multi-sensor data fusion and pervasive embedded computing. The main idea is to provide a generic architecture which supports a distributed online data fusion on an embedded system. Due to their high onboard processing and communication power our proposed architecture is designed to perform sophisticated data fusion tasks in realtime. Another goal of I-SENSE is to dynamically change the configuration, thus, to be able to react to changes in the systems environment. This paper describes ongoing work in developing necessary hard- and software components in order to perform realtime multi-level data fusion. We present the distributed I-SENSE platform and introduce our multi-level fusion framework. First experimental results on embedded image fusion demonstrates the feasibility of our approach
{"title":"I-SENSE: Intelligent Embedded Multi-Sensor Fusion","authors":"A. Klausner, B. Rinner, A. Tengg","doi":"10.1109/WISES.2006.329120","DOIUrl":"https://doi.org/10.1109/WISES.2006.329120","url":null,"abstract":"I-SENSE demonstrates the potential of combining the scientific research areas multi-sensor data fusion and pervasive embedded computing. The main idea is to provide a generic architecture which supports a distributed online data fusion on an embedded system. Due to their high onboard processing and communication power our proposed architecture is designed to perform sophisticated data fusion tasks in realtime. Another goal of I-SENSE is to dynamically change the configuration, thus, to be able to react to changes in the systems environment. This paper describes ongoing work in developing necessary hard- and software components in order to perform realtime multi-level data fusion. We present the distributed I-SENSE platform and introduce our multi-level fusion framework. First experimental results on embedded image fusion demonstrates the feasibility of our approach","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127638481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329117
R. Pedersen, Martin Schoeberl
In this paper we work on the balance between hardware and software implementation of a machine learning algorithm, which belongs to the area of statistical learning theory. We use system-on-chip technology to demonstrate the potential usefulness of moving the critical sections of an algorithm into HW: the so-called hardware/software balance. Our experiments show that the approach can achieve speedups using a complex machine learning algorithm called a support vector machine. The experiments are conducted on a real-time Java virtual machine named Java optimized processor
{"title":"An Embedded Support Vector Machine","authors":"R. Pedersen, Martin Schoeberl","doi":"10.1109/WISES.2006.329117","DOIUrl":"https://doi.org/10.1109/WISES.2006.329117","url":null,"abstract":"In this paper we work on the balance between hardware and software implementation of a machine learning algorithm, which belongs to the area of statistical learning theory. We use system-on-chip technology to demonstrate the potential usefulness of moving the critical sections of an algorithm into HW: the so-called hardware/software balance. Our experiments show that the approach can achieve speedups using a complex machine learning algorithm called a support vector machine. The experiments are conducted on a real-time Java virtual machine named Java optimized processor","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329115
R. Obermaisser, P. Peti
Integrated architectures in the automotive and avionic domain promise improved resource utilization and enable a better tactic coordination of application subsystems compared to federated systems. In order to support safety-critical application subsystems, an integrated architecture needs to support fault-tolerant strategies that enable the continued operation of the system in the presence of failures. The basis for the implementation and validation of fault-tolerant strategies is a fault hypothesis that identifies the fault containment regions, specifies the failure modes and provides realistic failure rate assumptions. This paper describes a fault hypothesis for integrated architectures, which takes into account the collocation of multiple software components on shared node computers. We argue in favor of a differentiation of fault containment regions for hardware and software faults. In addition, the fault hypothesis describes the assumptions concerning the respective frequencies of transient and permanent failures in consideration of recent semiconductor trends
{"title":"A Fault Hypothesis for Integrated Architectures","authors":"R. Obermaisser, P. Peti","doi":"10.1109/WISES.2006.329115","DOIUrl":"https://doi.org/10.1109/WISES.2006.329115","url":null,"abstract":"Integrated architectures in the automotive and avionic domain promise improved resource utilization and enable a better tactic coordination of application subsystems compared to federated systems. In order to support safety-critical application subsystems, an integrated architecture needs to support fault-tolerant strategies that enable the continued operation of the system in the presence of failures. The basis for the implementation and validation of fault-tolerant strategies is a fault hypothesis that identifies the fault containment regions, specifies the failure modes and provides realistic failure rate assumptions. This paper describes a fault hypothesis for integrated architectures, which takes into account the collocation of multiple software components on shared node computers. We argue in favor of a differentiation of fault containment regions for hardware and software faults. In addition, the fault hypothesis describes the assumptions concerning the respective frequencies of transient and permanent failures in consideration of recent semiconductor trends","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329114
Francisco Afonso, Carlos Alberto Silva, S. Montenegro, A. Tavares
Critical embedded systems need a dependable operating system and application. Despite all efforts to prevent and remove faults in system development, residual software faults usually persist. Therefore, critical systems need some sort of fault tolerance to deal with these faults and also with hardware faults at operation time. This work proposes fault-tolerant support mechanisms for the BOSS embedded operating system, based on the application of proven fault tolerance strategies by middleware control software which transparently delivers the added functionality to the application software. Special attention is taken to complexity control and resource constraints, targeting the needs of the embedded market
{"title":"Middleware Fault Tolerance Support for the BOSS Embedded Operating System","authors":"Francisco Afonso, Carlos Alberto Silva, S. Montenegro, A. Tavares","doi":"10.1109/WISES.2006.329114","DOIUrl":"https://doi.org/10.1109/WISES.2006.329114","url":null,"abstract":"Critical embedded systems need a dependable operating system and application. Despite all efforts to prevent and remove faults in system development, residual software faults usually persist. Therefore, critical systems need some sort of fault tolerance to deal with these faults and also with hardware faults at operation time. This work proposes fault-tolerant support mechanisms for the BOSS embedded operating system, based on the application of proven fault tolerance strategies by middleware control software which transparently delivers the added functionality to the application software. Special attention is taken to complexity control and resource constraints, targeting the needs of the embedded market","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116510674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329122
A. Hanzlik, A. Ademaj
In a previous work we have shown that by deploying a node with a high-quality oscillator (rate-master node) in each cluster of a real-time system, we can integrate internal and external clock synchronization by a combination of a distributed mechanism for clock state synchronization with a central mechanism for clock rate synchronization. By means of hardware and simulation experiments we have shown that this combination improves the precision of the global time base in single- and multi-cluster systems while reducing the need for high-quality oscillators for non-rate-master nodes. In the original approach all nodes, including the rate-master node, execute a fault-tolerant internal clock synchronization algorithm in course of which all nodes periodically adjust their local clocks by means of clock state correction. In this paper we analyze a derivative of the original algorithm in which the rate-master node does not take part in the internal clock synchronization algorithm. We study and discuss this approach for clock synchronization with regard to cluster precision, cluster drift rate and non-interference with external clock synchronization and multi-cluster clock synchronization
{"title":"A Composable Algorithm for Clock Synchronization in Multi-Cluster Real-Time Systems","authors":"A. Hanzlik, A. Ademaj","doi":"10.1109/WISES.2006.329122","DOIUrl":"https://doi.org/10.1109/WISES.2006.329122","url":null,"abstract":"In a previous work we have shown that by deploying a node with a high-quality oscillator (rate-master node) in each cluster of a real-time system, we can integrate internal and external clock synchronization by a combination of a distributed mechanism for clock state synchronization with a central mechanism for clock rate synchronization. By means of hardware and simulation experiments we have shown that this combination improves the precision of the global time base in single- and multi-cluster systems while reducing the need for high-quality oscillators for non-rate-master nodes. In the original approach all nodes, including the rate-master node, execute a fault-tolerant internal clock synchronization algorithm in course of which all nodes periodically adjust their local clocks by means of clock state correction. In this paper we analyze a derivative of the original algorithm in which the rate-master node does not take part in the internal clock synchronization algorithm. We study and discuss this approach for clock synchronization with regard to cluster precision, cluster drift rate and non-interference with external clock synchronization and multi-cluster clock synchronization","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127100633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329110
M. Bader, M. Gil, Robert Sablatnig, José-Enrique Simó-Ten, G. Benet, G. Novak, F. Blanes
Estimation of objects in a 3D space is a fundamental problem in computer vision and robotics. This paper describes an algorithm and its implementation for a vision module as a sensor of a biped robot (YABIRO). The embedded vision sensor is able to estimate the position of objects like spheres in 3D space. Objects are defined with their size and color in a model. The vision sensor detects the positions or at least the directions to the objects and stores them in a history. The algorithm includes a new voting system for detected objects, based on how trustable the detection was, and a new edge filter to terminate edges on the circle border for the circle detection. The systems frame rate depends on the area of interest and lies between 5 Hz and 20 Hz. With a mechanical size of 36times32mm it is smaller than a matchbox
{"title":"Embedded Real-Time Ball Detection Unit for the YABIRO Biped Robot","authors":"M. Bader, M. Gil, Robert Sablatnig, José-Enrique Simó-Ten, G. Benet, G. Novak, F. Blanes","doi":"10.1109/WISES.2006.329110","DOIUrl":"https://doi.org/10.1109/WISES.2006.329110","url":null,"abstract":"Estimation of objects in a 3D space is a fundamental problem in computer vision and robotics. This paper describes an algorithm and its implementation for a vision module as a sensor of a biped robot (YABIRO). The embedded vision sensor is able to estimate the position of objects like spheres in 3D space. Objects are defined with their size and color in a model. The vision sensor detects the positions or at least the directions to the objects and stores them in a history. The algorithm includes a new voting system for detected objects, based on how trustable the detection was, and a new edge filter to terminate edges on the circle border for the circle detection. The systems frame rate depends on the area of interest and lies between 5 Hz and 20 Hz. With a mechanical size of 36times32mm it is smaller than a matchbox","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"34 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115737340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329121
Peter Tawdross, A. König
Sensor electronics is ubiquitous in embedded systems, yet its performance is susceptible to static and dynamic deviations. Even costly and time consuming laser trimming still can't deal with all the occurring deviations. Recently, analog reconfigurable electronics offers a solution to compensate these effects. The state of the art uses genetic algorithm (GA) to find an arbitrary topology to fulfil the given specifications, which can cause hardware with unpredictable behavior. Considering the robustness of the reconfiguration approach, we used the particle swarm optimization (PSO) by Tawdross, P. and Konig, A. (2005) as an alternative to GA for reconfiguration of programmable sensor electronics by Tawdross, P. et al. (2005) on basic block level. In order to evolve a reliable hardware with predictable performance, standard circuit topologies are employed. In this paper, we abstract our design environment from amplifier level to the functional block level. We demonstrate our methodology by a reconfigurable 3-bit flash analog to digital convert (ADC), which can recover successfully from static and dynamic deviations
{"title":"Particle Swarm Optimization for Reconfigurable Sensor Electronics - Case Study: 3 Bit Flash ADC","authors":"Peter Tawdross, A. König","doi":"10.1109/WISES.2006.329121","DOIUrl":"https://doi.org/10.1109/WISES.2006.329121","url":null,"abstract":"Sensor electronics is ubiquitous in embedded systems, yet its performance is susceptible to static and dynamic deviations. Even costly and time consuming laser trimming still can't deal with all the occurring deviations. Recently, analog reconfigurable electronics offers a solution to compensate these effects. The state of the art uses genetic algorithm (GA) to find an arbitrary topology to fulfil the given specifications, which can cause hardware with unpredictable behavior. Considering the robustness of the reconfiguration approach, we used the particle swarm optimization (PSO) by Tawdross, P. and Konig, A. (2005) as an alternative to GA for reconfiguration of programmable sensor electronics by Tawdross, P. et al. (2005) on basic block level. In order to evolve a reliable hardware with predictable performance, standard circuit topologies are employed. In this paper, we abstract our design environment from amplifier level to the functional block level. We demonstrate our methodology by a reconfigurable 3-bit flash analog to digital convert (ADC), which can recover successfully from static and dynamic deviations","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133696793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329112
E. Kaniušas, Thomas Maier, H. Weiser, G. Varoneckas, L. Zakarevicius
The present paper introduces a patient-friendly embedded electrographic (ECG) amplifier. In contrast to the standard ECG amplifier, the presented system uses only two electrodes to insure unobtrusiveness and compact design. The abandoned third reference electrode and required low power consumption introduce problems in ECG signal preamplification and handling. In order to meet them, a novel adaptive cancellation of 50 Hz power line interference in combination with gain/attenuation controlling is designed and implemented. In particular, the interference is reduced by the use of a self-generated 50 Hz signal with an adoptively adjusted amplitude and phase. On the other hand, the gain/attenuation of the ECG signal is controlled in a way that the range of the analog-to-digital converters is efficiently used. The introduced ECG amplifier without the reference electrode facilitates the portable minimally obtrusive monitoring with potential possibilities of on-site diagnosis
{"title":"Embedded Electrocardiographic Amplifier without Reference Electrode","authors":"E. Kaniušas, Thomas Maier, H. Weiser, G. Varoneckas, L. Zakarevicius","doi":"10.1109/WISES.2006.329112","DOIUrl":"https://doi.org/10.1109/WISES.2006.329112","url":null,"abstract":"The present paper introduces a patient-friendly embedded electrographic (ECG) amplifier. In contrast to the standard ECG amplifier, the presented system uses only two electrodes to insure unobtrusiveness and compact design. The abandoned third reference electrode and required low power consumption introduce problems in ECG signal preamplification and handling. In order to meet them, a novel adaptive cancellation of 50 Hz power line interference in combination with gain/attenuation controlling is designed and implemented. In particular, the interference is reduced by the use of a self-generated 50 Hz signal with an adoptively adjusted amplitude and phase. On the other hand, the gain/attenuation of the ECG signal is controlled in a way that the range of the analog-to-digital converters is efficiently used. The introduced ECG amplifier without the reference electrode facilitates the portable minimally obtrusive monitoring with potential possibilities of on-site diagnosis","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128819598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329111
J. Kaiser, H. Piontek
This paper presents CODES (COsmic embedded DEvice Specifications) which allows to describe the properties of smart components. A component is a small autonomous device that encapsulates hardware, software and possibly mechanical parts. The interaction model for the components is based on a publisher/subscriber scheme in which well defined information objects - events - are produced and consumed. CODES provides a description for the smart components in the system related to the events which they produce and consume. Additionally, CODES is exploited by a set of an appropriate tools supporting the system developer with respect to different tasks: (1) CODES allows to keep the specification in compliance with the documentation and code; (2) CODES generates code skeletons to ease the programming task; and (3) CODES facilitates the integration of components in a larger system in which multiple components cooperate
{"title":"CODES: Supporting the development process in a publish/subscribe system","authors":"J. Kaiser, H. Piontek","doi":"10.1109/WISES.2006.329111","DOIUrl":"https://doi.org/10.1109/WISES.2006.329111","url":null,"abstract":"This paper presents CODES (COsmic embedded DEvice Specifications) which allows to describe the properties of smart components. A component is a small autonomous device that encapsulates hardware, software and possibly mechanical parts. The interaction model for the components is based on a publisher/subscriber scheme in which well defined information objects - events - are produced and consumed. CODES provides a description for the smart components in the system related to the events which they produce and consume. Additionally, CODES is exploited by a set of an appropriate tools supporting the system developer with respect to different tasks: (1) CODES allows to keep the specification in compliance with the documentation and code; (2) CODES generates code skeletons to ease the programming task; and (3) CODES facilitates the integration of components in a larger system in which multiple components cooperate","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"2674 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125621902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-06-30DOI: 10.1109/WISES.2006.329128
Marcus Venzke, Peng Kong, V. Turau
The paper presents a generic, high-level Java interface for the vertical integration of wireless sensor networks. The intuitive interfaces are implemented in a framework that is easy to use. The classes of the framework can be extended to meet the requirements of a wide range of applications. In particular, the framework supports sending packets to and receiving packets from nodes of the sensor network. Packet types are represented as Java classes generated from meta-data based on XML schema. This approach fosters short development cycles and provides the productivity needed in vertical integration applications. The ScatterWeb platform is used as a sample platform for sensor networks
{"title":"A Generic Java Interface for Vertical Integration of Wireless Sensor Networks","authors":"Marcus Venzke, Peng Kong, V. Turau","doi":"10.1109/WISES.2006.329128","DOIUrl":"https://doi.org/10.1109/WISES.2006.329128","url":null,"abstract":"The paper presents a generic, high-level Java interface for the vertical integration of wireless sensor networks. The intuitive interfaces are implemented in a framework that is easy to use. The classes of the framework can be extended to meet the requirements of a wide range of applications. In particular, the framework supports sending packets to and receiving packets from nodes of the sensor network. Packet types are represented as Java classes generated from meta-data based on XML schema. This approach fosters short development cycles and provides the productivity needed in vertical integration applications. The ScatterWeb platform is used as a sample platform for sensor networks","PeriodicalId":344061,"journal":{"name":"2006 International Workshop on Intelligent Solutions in Embedded Systems","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131027553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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