The solution of many engineering and scientific problems requires the exploration of a huge n-dimensional design space. Typical approaches rely on an abstract problem model consisting of a system model (description of the problem's variable couplings) and an optimization specification defining the objectives as well as the constraints bounding the design space. Advances in solver technologies enabled to efficiently search the solution space, however the diversity of the approaches led to problem descriptions that are difficult to reuse, as well as to solutions that are hard to compare. Our Exploration Meta-Model (EMM) addresses this issue by providing a unified language for optimization specifications that is a well-defined basis for model-based implementations of solver-independent design-space exploration (DSE) tool-chains. The EMM is a light-weight framework that allows to a) describe optimization specifications independent of particular optimization methods and solvers, b) relate solutions and optimization specifications, and c) define domain profiles that provide high-level optimization specifications that ease the adoption of automated DSE by domain experts. The applicability of our framework to different optimization methods is demonstrated by applying it to the generic vector optimization problem and to single-objective linear programs. The EMM's support to relate optimization results to input specifications is exercised for the Opt4J framework. Finally, a profile for real-time embedded systems demonstrates how the EMM can be tailored to specific domains.
{"title":"A Lightweight Design Space Exploration and Optimization Language","authors":"Alexander Diewald, S. Voss, S. Barner","doi":"10.1145/2906363.2906367","DOIUrl":"https://doi.org/10.1145/2906363.2906367","url":null,"abstract":"The solution of many engineering and scientific problems requires the exploration of a huge n-dimensional design space. Typical approaches rely on an abstract problem model consisting of a system model (description of the problem's variable couplings) and an optimization specification defining the objectives as well as the constraints bounding the design space. Advances in solver technologies enabled to efficiently search the solution space, however the diversity of the approaches led to problem descriptions that are difficult to reuse, as well as to solutions that are hard to compare. Our Exploration Meta-Model (EMM) addresses this issue by providing a unified language for optimization specifications that is a well-defined basis for model-based implementations of solver-independent design-space exploration (DSE) tool-chains. The EMM is a light-weight framework that allows to a) describe optimization specifications independent of particular optimization methods and solvers, b) relate solutions and optimization specifications, and c) define domain profiles that provide high-level optimization specifications that ease the adoption of automated DSE by domain experts. The applicability of our framework to different optimization methods is demonstrated by applying it to the generic vector optimization problem and to single-objective linear programs. The EMM's support to relate optimization results to input specifications is exercised for the Opt4J framework. Finally, a profile for real-time embedded systems demonstrates how the EMM can be tailored to specific domains.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129739324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many embedded multiprocessor systems have hard real-time requirements which should be guaranteed at design time by means of analytical techniques that cover all cases. It is desirable to evaluate the correctness and tightness of the analysis results by means of simulation. However, verification of the analytically obtained results is hampered by the lack of a fast high level simulation approach that supports task scheduling and that does not produce pessimistic simulation traces. In this paper we present HAPI, an event driven simulator for the evaluation of the results of real-time analysis techniques for task graphs executed on multiprocessor systems that support processor sharing. HAPI produces simulation traces that are pessimistic to reality and optimistic to temporal analysis. It can be consequently used to detect optimistic, i.e. incorrect, analysis results. Several task scheduling policies are supported by HAPI such as fixed priority preemptive, time-division multiplex and round-robin. Preemptive task scheduling decisions are simulated which enables to study the cause of delayed task finishes and thereby helps to identify overly pessimistic analysis results. We demonstrate the applicability of the simulator using a number of didactic examples and a WLAN 802.11p application.
{"title":"HAPI: An Event-Driven Simulator for Real-Time Multiprocessor Systems","authors":"P. Kurtin, J. Hausmans, M. Bekooij","doi":"10.1145/2906363.2906381","DOIUrl":"https://doi.org/10.1145/2906363.2906381","url":null,"abstract":"Many embedded multiprocessor systems have hard real-time requirements which should be guaranteed at design time by means of analytical techniques that cover all cases. It is desirable to evaluate the correctness and tightness of the analysis results by means of simulation. However, verification of the analytically obtained results is hampered by the lack of a fast high level simulation approach that supports task scheduling and that does not produce pessimistic simulation traces. In this paper we present HAPI, an event driven simulator for the evaluation of the results of real-time analysis techniques for task graphs executed on multiprocessor systems that support processor sharing. HAPI produces simulation traces that are pessimistic to reality and optimistic to temporal analysis. It can be consequently used to detect optimistic, i.e. incorrect, analysis results. Several task scheduling policies are supported by HAPI such as fixed priority preemptive, time-division multiplex and round-robin. Preemptive task scheduling decisions are simulated which enables to study the cause of delayed task finishes and thereby helps to identify overly pessimistic analysis results. We demonstrate the applicability of the simulator using a number of didactic examples and a WLAN 802.11p application.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Weichslgartner, S. Wildermann, J. Götzfried, F. Freiling, M. Glaß, J. Teich
Different applications concurrently running on modern MPSoCs can interfere with each other when they use shared resources. This interference can cause side channels, i.e., sources of unintended information flow between applications. To prevent such side channels, we propose a hybrid mapping methodology that attempts to ensure spatial isolation, i.e., a mutually-exclusive allocation of resources to applications in the MPSoC. At design time and as a first step, we compute compact and connected application mappings (called shapes). In a second step, run-time management uses this information to map multiple spatially segregated shapes to the architecture. We present and evaluate a (fast) heuristic and an (exact) SAT-based mapper, demonstrating the viability of the approach.
{"title":"Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs","authors":"A. Weichslgartner, S. Wildermann, J. Götzfried, F. Freiling, M. Glaß, J. Teich","doi":"10.1145/2906363.2906370","DOIUrl":"https://doi.org/10.1145/2906363.2906370","url":null,"abstract":"Different applications concurrently running on modern MPSoCs can interfere with each other when they use shared resources. This interference can cause side channels, i.e., sources of unintended information flow between applications. To prevent such side channels, we propose a hybrid mapping methodology that attempts to ensure spatial isolation, i.e., a mutually-exclusive allocation of resources to applications in the MPSoC. At design time and as a first step, we compute compact and connected application mappings (called shapes). In a second step, run-time management uses this information to map multiple spatially segregated shapes to the architecture. We present and evaluate a (fast) heuristic and an (exact) SAT-based mapper, demonstrating the viability of the approach.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.
{"title":"Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems","authors":"Arno Luppold, C. Kittsteiner, H. Falk","doi":"10.1145/2906363.2906369","DOIUrl":"https://doi.org/10.1145/2906363.2906369","url":null,"abstract":"To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the program's worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the program's memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116362134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We demonstrate how static, energy-efficient, compiler-generated schedules for independent, parallelizable tasks on parallel machines can be improved by modeling idle power. We assume that the static power consumption of a core comprises a notable fraction of the core's total power, which is more and more often the case. The improvement is achieved by optimally packing cores when deciding about core allocation, mapping and DVFS for each task so that all unused cores can be switched off and overall energy usage is minimized. We evaluate our proposal with a benchmark suite of task collections, and compare the resulting schedules with an optimal scheduler that does not take idle power and core switch-off into account. We find that we can reduce energy consumption by 66% for mostly sequential tasks on many cores and by up to 91% for a realistic multicore processor model.
{"title":"Energy-Optimized Static Scheduling for Many-Cores with Task Parallelization, DVFS and Core Consolidation","authors":"Nicolas Melot, C. Kessler, J. Keller","doi":"10.1145/2906363.2906376","DOIUrl":"https://doi.org/10.1145/2906363.2906376","url":null,"abstract":"We demonstrate how static, energy-efficient, compiler-generated schedules for independent, parallelizable tasks on parallel machines can be improved by modeling idle power. We assume that the static power consumption of a core comprises a notable fraction of the core's total power, which is more and more often the case. The improvement is achieved by optimally packing cores when deciding about core allocation, mapping and DVFS for each task so that all unused cores can be switched off and overall energy usage is minimized. We evaluate our proposal with a benchmark suite of task collections, and compare the resulting schedules with an optimal scheduler that does not take idle power and core switch-off into account. We find that we can reduce energy consumption by 66% for mostly sequential tasks on many cores and by up to 91% for a realistic multicore processor model.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127878872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deshya Wijesundera, Alok Prakash, S. Lam, T. Srikanthan
The large number of possible configurations in modern soft-core processors make it tedious and time consuming to select the optimal configuration for a given application. In this paper, we propose a framework for rapid area-efficient customization of soft-core processors that exploits the dependencies between the various configuration options to prune the design space. Additionally, the proposed technique relies on rapid and accurate estimation models instead of the time consuming synthesis and execution techniques proposed in the existing work. Experimental results based on hand-coded applications and applications from the popular CHStone benchmark suite show that the proposed framework can rapidly and reliably select the best processor configuration for a given application and save an average of 47.58% area over the processor with all the configuration options enabled while achieving similar performance.
{"title":"Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors","authors":"Deshya Wijesundera, Alok Prakash, S. Lam, T. Srikanthan","doi":"10.1145/2906363.2906385","DOIUrl":"https://doi.org/10.1145/2906363.2906385","url":null,"abstract":"The large number of possible configurations in modern soft-core processors make it tedious and time consuming to select the optimal configuration for a given application. In this paper, we propose a framework for rapid area-efficient customization of soft-core processors that exploits the dependencies between the various configuration options to prune the design space. Additionally, the proposed technique relies on rapid and accurate estimation models instead of the time consuming synthesis and execution techniques proposed in the existing work. Experimental results based on hand-coded applications and applications from the popular CHStone benchmark suite show that the proposed framework can rapidly and reliably select the best processor configuration for a given application and save an average of 47.58% area over the processor with all the configuration options enabled while achieving similar performance.","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115044225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","authors":"","doi":"10.1145/2906363","DOIUrl":"https://doi.org/10.1145/2906363","url":null,"abstract":"","PeriodicalId":344390,"journal":{"name":"Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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