Pub Date : 1979-06-01DOI: 10.1049/IJ-CDT.1979.0023
A. Davies
Multiplication algorithms which are appropriate for 8-bit microprocessors are discussed, particularly within the context of signal-processing needs, where minimisation of execution time is important. The trade-offs which exist between minimum memory, minimum execution time and minimum cost are discussed in detail, and specific examples based on the Z80 processor are included to provide a quantitative comparison of the alternatives.
{"title":"Trade-offs in fixed-point multiplication algorithms for microprocesors","authors":"A. Davies","doi":"10.1049/IJ-CDT.1979.0023","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0023","url":null,"abstract":"Multiplication algorithms which are appropriate for 8-bit microprocessors are discussed, particularly within the context of signal-processing needs, where minimisation of execution time is important. The trade-offs which exist between minimum memory, minimum execution time and minimum cost are discussed in detail, and specific examples based on the Z80 processor are included to provide a quantitative comparison of the alternatives.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1979-06-01DOI: 10.1049/IJ-CDT.1979.0024
J. Gosling, D. Kinniment, D. Edwards
Large-scale integration has permitted the design of 4×4, 8×8 and even 16×16 multiplier systems on a single chip. This paper discusses methods of multiplication and identifies a method which is particularly suited to bit-slice integration and the multiplication of longer words such as 64 × 64 bits. A 2-bit slice has been designed on an uncommitted logic array, and these have been built into and tested in a 16 × 16 bit system. The results of the experiment are reported, and extrapolation from these show that a 64 × 64 bit multiplier can be built with 71 integrated-circuit chips to provide a multiplication time of less than 290 ns. Other developments are indicated which show that a reduction of these figures to 56 chips and 115 ns can be achieved. An alternative design using the same u.l.a. is found to be more expensive at 128 chips, but enables the time to be reduced to 80 ns. A number of other multipliers are also discussed, several of which would be an economical proposition as a high-performance add-on unit for many mini- and microcomputers. However, the u.l.a. design proposed here is found to be the most cost-effective system.
{"title":"Uncommitted logic array which provides cost-effective multiplication even for long words","authors":"J. Gosling, D. Kinniment, D. Edwards","doi":"10.1049/IJ-CDT.1979.0024","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0024","url":null,"abstract":"Large-scale integration has permitted the design of 4×4, 8×8 and even 16×16 multiplier systems on a single chip. This paper discusses methods of multiplication and identifies a method which is particularly suited to bit-slice integration and the multiplication of longer words such as 64 × 64 bits. A 2-bit slice has been designed on an uncommitted logic array, and these have been built into and tested in a 16 × 16 bit system. The results of the experiment are reported, and extrapolation from these show that a 64 × 64 bit multiplier can be built with 71 integrated-circuit chips to provide a multiplication time of less than 290 ns. Other developments are indicated which show that a reduction of these figures to 56 chips and 115 ns can be achieved. An alternative design using the same u.l.a. is found to be more expensive at 128 chips, but enables the time to be reduced to 80 ns. A number of other multipliers are also discussed, several of which would be an economical proposition as a high-performance add-on unit for many mini- and microcomputers. However, the u.l.a. design proposed here is found to be the most cost-effective system.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132673598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The analysis of baseband digital transmission systems is reviewed. Modifications to the standard methods are proposed, which lead to fairly simple algebraic expressions for system performance in a number of important cases. These results are used to investigate the relations between system performance and design parameters, and the conditions under which optimum performance may be obtained are investigated.
{"title":"Analysis and design of digital transmission systems","authors":"D. Ingram","doi":"10.1049/IJ-CDT:19790025","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790025","url":null,"abstract":"The analysis of baseband digital transmission systems is reviewed. Modifications to the standard methods are proposed, which lead to fairly simple algebraic expressions for system performance in a number of important cases. These results are used to investigate the relations between system performance and design parameters, and the conditions under which optimum performance may be obtained are investigated.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127885934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes the use of partial double and triple precision with residue retention as a new arithmetic structure for solving differential equations on microprocessors. It is shown that a residue register, which is the distinguishing feature of the digital differential analyser, improves solution accuracy considerably by suppressing the accumulation of roundoff error, which is generally a problem on short-wordlength machines. Both theory and simulation reveal that by employing partial triple precision with residue retention, better than double-precision accuracy may be achieved with only a single-precision multiplication, whereas, without residue retention, single-precision accuracy only is possible.
{"title":"Partial double precision with residue retention: a new approach to solving differential equations on microprocessors","authors":"G. McCrea, I. Witten","doi":"10.1049/IJ-CDT:19790021","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790021","url":null,"abstract":"This paper proposes the use of partial double and triple precision with residue retention as a new arithmetic structure for solving differential equations on microprocessors. It is shown that a residue register, which is the distinguishing feature of the digital differential analyser, improves solution accuracy considerably by suppressing the accumulation of roundoff error, which is generally a problem on short-wordlength machines. Both theory and simulation reveal that by employing partial triple precision with residue retention, better than double-precision accuracy may be achieved with only a single-precision multiplication, whereas, without residue retention, single-precision accuracy only is possible.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132882424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1979-04-01DOI: 10.1049/IJ-CDT.1979.0016
M. Lecouffe
This paper presents MAUD, a parallel processor based on data-driven execution with dynamic behaviour at the execution level. MAUD is a dynamic single-assignment machine (`Machine d' Assignation Unique Dynamique'). Data-driven sequencing control is used for a producer-consumer model applied to one or several kinds of objects. The chosen objects are called blocks. The dynamic behaviour is characterised by the ability to create new blocks during program execution. The paper gives a functional description in which the different elements of the system are introduced. A suitable architecture is then proposed, based on a novel type of memory realisable with l.s.i. circuit technology.
本文提出了一种基于数据驱动执行的并行处理器MAUD，它在执行层具有动态行为。MAUD是一个动态的单分配机器(' machine d' Assignation Unique Dynamique')。数据驱动的排序控制用于应用于一种或几种对象的生产者-消费者模型。所选择的对象称为块。动态行为的特点是能够在程序执行期间创建新的块。本文给出了系统的功能描述，介绍了系统的各个组成部分。然后提出了一个合适的架构，基于一种新型的存储器可实现的l.s.i.电路技术。
{"title":"MAUD: a dynamic single-assignment system","authors":"M. Lecouffe","doi":"10.1049/IJ-CDT.1979.0016","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0016","url":null,"abstract":"This paper presents MAUD, a parallel processor based on data-driven execution with dynamic behaviour at the execution level. MAUD is a dynamic single-assignment machine (`Machine d' Assignation Unique Dynamique'). Data-driven sequencing control is used for a producer-consumer model applied to one or several kinds of objects. The chosen objects are called blocks. The dynamic behaviour is characterised by the ability to create new blocks during program execution. The paper gives a functional description in which the different elements of the system are introduced. A suitable architecture is then proposed, based on a novel type of memory realisable with l.s.i. circuit technology.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126654915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1979-04-01DOI: 10.1049/IJ-CDT.1979.0019
M. Beale, T. Tozer
A class of composite sequences is described, which may have application in spread-spectrum multiple-access systems. Expressions are derived for their cross- and autocorrelation properties in terms of constituent sequences, and are developed further for the particular case when these are maximal-length sequences.
{"title":"A class of composite sequences for spread-spectrum communications","authors":"M. Beale, T. Tozer","doi":"10.1049/IJ-CDT.1979.0019","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0019","url":null,"abstract":"A class of composite sequences is described, which may have application in spread-spectrum multiple-access systems. Expressions are derived for their cross- and autocorrelation properties in terms of constituent sequences, and are developed further for the particular case when these are maximal-length sequences.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122541983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1979-04-01DOI: 10.1049/IJ-CDT.1979.0014
B. Batchelor
The application of an interactive image-analysis system (Susie) is demonstrated on a variety of tasks in automatic visual inspection, including: (a) the existential inspection and pitch measurement of female screw threads; (b) checking, the legibility of printing on tablets; (c) the enhancement of visibility of industrial radiographs; (d) detecting defects on polished metal surfaces(hydraulics cylinder bores and bright, extruded copper bars); (e) analysing the texture of machined metal surfaces; (f) locating the ends of fibrelike objects (asbestos) viewed under a microscope, as a prelude to counting them or measuring their lengths; and (g) counting, sorting and recognising defects in pressed artefacts, strewn haphazardly onto a table. Susie is ideally suited for evaluating such problems and for prototyping special-purpose visual-inspection systems. It is easy to learn to use Susie and, given suitable optics, an experienced image analyst can very quickly understand the nature of the pictures he is given and develop a suitable strategy for processing them.
{"title":"Interactive image analysis as a prototyping tool for industrial inspection","authors":"B. Batchelor","doi":"10.1049/IJ-CDT.1979.0014","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0014","url":null,"abstract":"The application of an interactive image-analysis system (Susie) is demonstrated on a variety of tasks in automatic visual inspection, including: (a) the existential inspection and pitch measurement of female screw threads; (b) checking, the legibility of printing on tablets; (c) the enhancement of visibility of industrial radiographs; (d) detecting defects on polished metal surfaces(hydraulics cylinder bores and bright, extruded copper bars); (e) analysing the texture of machined metal surfaces; (f) locating the ends of fibrelike objects (asbestos) viewed under a microscope, as a prelude to counting them or measuring their lengths; and (g) counting, sorting and recognising defects in pressed artefacts, strewn haphazardly onto a table. Susie is ideally suited for evaluating such problems and for prototyping special-purpose visual-inspection systems. It is easy to learn to use Susie and, given suitable optics, an experienced image analyst can very quickly understand the nature of the pictures he is given and develop a suitable strategy for processing them.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132502082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.
{"title":"Parallel fault-tolerant computation structure","authors":"Z. Segall, M. Yoeli, E. Strasbourger","doi":"10.1049/IJ-CDT:19790018","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790018","url":null,"abstract":"A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126397547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Book review: Logical Design of Digital Systems","authors":"L. G. Bental","doi":"10.1049/IJ-CDT:19790017","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790017","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Entering the non-von-neumann era","authors":"F. G. Heath","doi":"10.1049/IJ-CDT:19790012","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790012","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124506304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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