We consider the problem of error detection in a process of computation of a polynomial over the field of complex numbers or over GF(p). By errors we mean errors in the text of a program or `stuck-at? errors in a device computing a polynomial. For error detection we use linear checks constructed by the technique of Fourier transformation over the group of binary vectors. Complexity estimations, optimal checks and estimations of the error-correcting capability of these checks are obtained.
{"title":"Error detection for polynomial computations","authors":"M. Karpovsky","doi":"10.1049/IJ-CDT:19790011","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19790011","url":null,"abstract":"We consider the problem of error detection in a process of computation of a polynomial over the field of complex numbers or over GF(p). By errors we mean errors in the text of a program or `stuck-at? errors in a device computing a polynomial. For error detection we use linear checks constructed by the technique of Fourier transformation over the group of binary vectors. Complexity estimations, optimal checks and estimations of the error-correcting capability of these checks are obtained.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1979-02-01DOI: 10.1049/IJ-CDT.1979.0009
I. Aleksander, T. Stonham
About 12 years of work with a specific type of learning pattern-recognition system are reviewed. The principles and characteristics of the scheme, which is based on random-access-memory implementation, are discussed in some detail. Methods of improving performance and cost-optimising pattern recognisers are presented, together with case studies in a variety of fields including the recognition of alphanumerics, chemical data and faults in digital circuit boards.
{"title":"Guide to pattern recognition using random-access memories","authors":"I. Aleksander, T. Stonham","doi":"10.1049/IJ-CDT.1979.0009","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1979.0009","url":null,"abstract":"About 12 years of work with a specific type of learning pattern-recognition system are reviewed. The principles and characteristics of the scheme, which is based on random-access-memory implementation, are discussed in some detail. Methods of improving performance and cost-optimising pattern recognisers are presented, together with case studies in a variety of fields including the recognition of alphanumerics, chemical data and faults in digital circuit boards.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1979-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NCC 78: Los angeles, Calif., USA, June 1978","authors":"R. Ibbett","doi":"10.1049/IJ-CDT:19780037","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780037","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132822714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An operator is described which is directly related to the Boolean difference. It is shown that all orders of Boolean difference may be derived under this operator, in one pass, by a simple manipulation in the Hadamard-transform domain. Application of this method to functions containing intermediate states is considered. The operator is important in the fields of digital-circuit fault diagnosis and synthesis.
{"title":"The generalised dyadic differentiator and its application to 2-valued functions defined on an n-space","authors":"C. R. Edwards","doi":"10.1049/IJ-CDT:19780040","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780040","url":null,"abstract":"An operator is described which is directly related to the Boolean difference. It is shown that all orders of Boolean difference may be derived under this operator, in one pass, by a simple manipulation in the Hadamard-transform domain. Application of this method to functions containing intermediate states is considered. The operator is important in the fields of digital-circuit fault diagnosis and synthesis.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123063905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-10-01DOI: 10.1049/IJ-CDT.1978.0036
S. Shrivastava
{"title":"8th annual international conference on fault-tolerant computing","authors":"S. Shrivastava","doi":"10.1049/IJ-CDT.1978.0036","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0036","url":null,"abstract":"","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116098952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the speed of integrated circuits improves, the contribution of the interconnections between the circuits becomes more important and may be the dominant factor in the system performance. To establish a criterion for comparison of future developments, some current construction techniques are examined in detail, and the connection distances plotted as a function of the size of the subunits connected. It is shown that the connection distances vary approximately as the square root of the number of chips to be interconnected, although this relationship can be improved by careful layout and physical design of the system. To make a further significant improvement in packing density, it is necessary to remove the packages from the integrated circuits and mount several together on a common assembly. A memory system using such techniques is compared with previous systems, and it is shown that with a basic circuit-speed improvement of a factor of 3.8, the overall system speed may only be improved by a factor of 3 without packaging improvements, but that an improvement of 4.4 times can be obtained with better packaging.
{"title":"Influence of circuit layout and packaging on fast computer performance","authors":"D. Kinniment, D. Edwards","doi":"10.1049/IJ-CDT:19780039","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780039","url":null,"abstract":"As the speed of integrated circuits improves, the contribution of the interconnections between the circuits becomes more important and may be the dominant factor in the system performance. To establish a criterion for comparison of future developments, some current construction techniques are examined in detail, and the connection distances plotted as a function of the size of the subunits connected. It is shown that the connection distances vary approximately as the square root of the number of chips to be interconnected, although this relationship can be improved by careful layout and physical design of the system. To make a further significant improvement in packing density, it is necessary to remove the packages from the integrated circuits and mount several together on a common assembly. A memory system using such techniques is compared with previous systems, and it is shown that with a basic circuit-speed improvement of a factor of 3.8, the overall system speed may only be improved by a factor of 3 without packaging improvements, but that an improvement of 4.4 times can be obtained with better packaging.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127781898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-10-01DOI: 10.1049/IJ-CDT.1978.0045
B. Batchelor
Nearly all of the previous work in visual pattern recognition has been based upon Cartesian images, that is those in which addressing is performed using Cartesian co-ordinates. In many instances circular patterns are evident and, in such cases, polar-co-ordinate addressing is both more natural and more convenient to use. The paper lists various applications areas which generate such pictures and chief among these is theautomatic visual inspection of industrial artefacts. Several techniques for digitising polar images are presented, including flying-spot scanners, rotating-image methods, and spiral-scan television. A variety of `polar? picture-processing techniques are discussed, including: (a) tangential lowpass and highpass filtering of polar images (b) radial lowpass and highpass filtering of polar images (c) `circular? filtering of Cartesian images (d) rectangular filtering of polar images (e) chain-coding of polar images (f) correlation in polar images (g) frequency and sequency analysis (h) gradient operators (i) integration along circular or radial paths (j) finding the centre of a circular picture
{"title":"Circular pictures, their digitisation and processing","authors":"B. Batchelor","doi":"10.1049/IJ-CDT.1978.0045","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0045","url":null,"abstract":"Nearly all of the previous work in visual pattern recognition has been based upon Cartesian images, that is those in which addressing is performed using Cartesian co-ordinates. In many instances circular patterns are evident and, in such cases, polar-co-ordinate addressing is both more natural and more convenient to use. The paper lists various applications areas which generate such pictures and chief among these is theautomatic visual inspection of industrial artefacts. Several techniques for digitising polar images are presented, including flying-spot scanners, rotating-image methods, and spiral-scan television. A variety of `polar? picture-processing techniques are discussed, including: (a) tangential lowpass and highpass filtering of polar images (b) radial lowpass and highpass filtering of polar images (c) `circular? filtering of Cartesian images (d) rectangular filtering of polar images (e) chain-coding of polar images (f) correlation in polar images (g) frequency and sequency analysis (h) gradient operators (i) integration along circular or radial paths (j) finding the centre of a circular picture","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116032478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-10-01DOI: 10.1049/IJ-CDT.1978.0042
A. M. Lloyd
A logic-synthesis procedure is presented which can be performed by simple arithmetic operations in the spectral domain. The procedure may be readily programmed, and has a major advantage over Quine-McClusky type design algorthms in that the larger a factor in a synthesis then the fewer the number of components which have to be considered. Further, being an arithmetic rather than a geometric type procedure, a limit in the number of inputs which may be handled, which occurs in geometric procedures, is not present.
{"title":"Spectral addition techniques for the synthesis of multivariable logic networks","authors":"A. M. Lloyd","doi":"10.1049/IJ-CDT.1978.0042","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0042","url":null,"abstract":"A logic-synthesis procedure is presented which can be performed by simple arithmetic operations in the spectral domain. The procedure may be readily programmed, and has a major advantage over Quine-McClusky type design algorthms in that the larger a factor in a synthesis then the fewer the number of components which have to be considered. Further, being an arithmetic rather than a geometric type procedure, a limit in the number of inputs which may be handled, which occurs in geometric procedures, is not present.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1978-10-01DOI: 10.1049/IJ-CDT.1978.0046
A. Clark
The paper considers four novel decoders that come close to achieving minimum-distance decoding of convolutional codes, but without requiring nearly as much storage or nearly as many operations per received data symbol as does the Viterbi-algorithm decoder. The methods of operation of the decoders are first described and the results of computer simulation tests are then presented, comparing the tolerances of the decoders to additive white Gaussian noise with that of a Viterbi-algorithm decoder. Four different rate½ -binary convolutional codes and three different distance measures are used in the tests.
{"title":"Minimum-distance decoding of binary convolutional codes","authors":"A. Clark","doi":"10.1049/IJ-CDT.1978.0046","DOIUrl":"https://doi.org/10.1049/IJ-CDT.1978.0046","url":null,"abstract":"The paper considers four novel decoders that come close to achieving minimum-distance decoding of convolutional codes, but without requiring nearly as much storage or nearly as many operations per received data symbol as does the Viterbi-algorithm decoder. The methods of operation of the decoders are first described and the results of computer simulation tests are then presented, comparing the tolerances of the decoders to additive white Gaussian noise with that of a Viterbi-algorithm decoder. Four different rate½ -binary convolutional codes and three different distance measures are used in the tests.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131195242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The multitude of computer input-output devices currently marketed, and their decreasing cost, often raises problems of transfer of information between different media. These are aggravated by the ready availability of low-cost processing power in the form of mini- and micro-computers, which encourage the development of many separate computer configurations, each with their own input-output facilities. Processor-processor links using existing input-output channels constitute a cheap and simple way of overcoming these incompatibilities. This paper discusses the software and hardware technology for handling such links, placing emphasis on simple, easily-implementable protocols and hardware rather than on maximum bandwidth utilisation and automatic error correction.
{"title":"Processor-processor dialogue through existing input-output channels","authors":"I. Witten, Richard L. Jenkins","doi":"10.1049/IJ-CDT:19780038","DOIUrl":"https://doi.org/10.1049/IJ-CDT:19780038","url":null,"abstract":"The multitude of computer input-output devices currently marketed, and their decreasing cost, often raises problems of transfer of information between different media. These are aggravated by the ready availability of low-cost processing power in the form of mini- and micro-computers, which encourage the development of many separate computer configurations, each with their own input-output facilities. Processor-processor links using existing input-output channels constitute a cheap and simple way of overcoming these incompatibilities. This paper discusses the software and hardware technology for handling such links, placing emphasis on simple, easily-implementable protocols and hardware rather than on maximum bandwidth utilisation and automatic error correction.","PeriodicalId":344610,"journal":{"name":"Iee Journal on Computers and Digital Techniques","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1978-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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