The simulation of the dynamics of the blood flow in the venous system of the lower limb is an important tool for supporting clinical research and for suggesting possible treatments for many diseases, e.g. for enhancing the surgical treatment of chronic venous insufficiency (CVI). Nevertheless the accuracy of the simulation of the blood flow is strictly related to the morphological data characterizing the investigated venous system. Although some of these data can be extracted from the observation of the real blood flow of a patient, e.g. through the acquisition of a set of images, the extraction of such values is often performed in a manual way, so the need for the automatic induction of parameters arises. The paper presents a software module that allows the semiautomatic acquisition of the morphological data of the venous system of a patient. The tool, developed as a plugin of the ImageJ imaging platform, receives in input a DICOM file containing the computerized tomography (CT) of the vessels network of the lower limb, and produces in a semi-automatic way a weighted graph of the network. This model can be used as the input for a subsequent simulation of the system.
{"title":"A Tool for the Semiautomatic Acquisition of the Morphological Data of Blood Vessel Networks","authors":"M. Cannataro, P. Guzzi, G. Tradigo, P. Veltri","doi":"10.1109/ISPA.2008.120","DOIUrl":"https://doi.org/10.1109/ISPA.2008.120","url":null,"abstract":"The simulation of the dynamics of the blood flow in the venous system of the lower limb is an important tool for supporting clinical research and for suggesting possible treatments for many diseases, e.g. for enhancing the surgical treatment of chronic venous insufficiency (CVI). Nevertheless the accuracy of the simulation of the blood flow is strictly related to the morphological data characterizing the investigated venous system. Although some of these data can be extracted from the observation of the real blood flow of a patient, e.g. through the acquisition of a set of images, the extraction of such values is often performed in a manual way, so the need for the automatic induction of parameters arises. The paper presents a software module that allows the semiautomatic acquisition of the morphological data of the venous system of a patient. The tool, developed as a plugin of the ImageJ imaging platform, receives in input a DICOM file containing the computerized tomography (CT) of the vessels network of the lower limb, and produces in a semi-automatic way a weighted graph of the network. This model can be used as the input for a subsequent simulation of the system.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption has become one of the most critical concerns for processor design. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose simple models for analysing algorithms that reflect the energy-time trade-offs of CMOS circuits. Using these models, we derive lower bounds for the energy-constrained execution time of sorting, addition and multiplication, and we present algorithms that meet these bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth.
{"title":"Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds","authors":"B. Bingham, M. Greenstreet","doi":"10.1109/ISPA.2008.127","DOIUrl":"https://doi.org/10.1109/ISPA.2008.127","url":null,"abstract":"Power consumption has become one of the most critical concerns for processor design. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose simple models for analysing algorithms that reflect the energy-time trade-offs of CMOS circuits. Using these models, we derive lower bounds for the energy-constrained execution time of sorting, addition and multiplication, and we present algorithms that meet these bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.
{"title":"DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor","authors":"Y. Dou, Lin Deng, Jinhui Xu, Yi Zheng","doi":"10.1109/ISPA.2008.54","DOIUrl":"https://doi.org/10.1109/ISPA.2008.54","url":null,"abstract":"The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-10DOI: 10.1504/IJHPCN.2012.046383
A. A. Zain, P. Trinder, K. Hammond
This paper describes a very high-level approach that aims to orchestrate sequential components written using high-level domain-specific programming into high-performance parallel applications. By achieving this goal, we hope to make parallel programming more accessible to experts in mathematics, engineering and other domains. A key feature of our approach is that parallelism is achieved without any modification to the underlying sequential computational algebra systems, or to the user-level components: rather, all orchestration is performed at an outer level, with sequential components linked through a standard communication protocol, the Symbolic Computing Software Composability Protocol, SCSCP. Despite the generality of our approach, our results show that we are able to achieve very good, and even, in some cases, super-linear, speedups on clusters of commodity workstations: up to a factor of 33.4 on a 28-processor cluster. We are, moreover, able to parallelise a wider variety of problem, and achieve higher performance than typical specialist parallel computational algebra implementations.
{"title":"Parallelism without Pain: Orchestrating Computational Algebra Components into a High-Performance Parallel System","authors":"A. A. Zain, P. Trinder, K. Hammond","doi":"10.1504/IJHPCN.2012.046383","DOIUrl":"https://doi.org/10.1504/IJHPCN.2012.046383","url":null,"abstract":"This paper describes a very high-level approach that aims to orchestrate sequential components written using high-level domain-specific programming into high-performance parallel applications. By achieving this goal, we hope to make parallel programming more accessible to experts in mathematics, engineering and other domains. A key feature of our approach is that parallelism is achieved without any modification to the underlying sequential computational algebra systems, or to the user-level components: rather, all orchestration is performed at an outer level, with sequential components linked through a standard communication protocol, the Symbolic Computing Software Composability Protocol, SCSCP. Despite the generality of our approach, our results show that we are able to achieve very good, and even, in some cases, super-linear, speedups on clusters of commodity workstations: up to a factor of 33.4 on a 28-processor cluster. We are, moreover, able to parallelise a wider variety of problem, and achieve higher performance than typical specialist parallel computational algebra implementations.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122923231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xinjie Lv, Tian Yang, Zaifei Liao, Xin Li, Yongyan Wang, W. Liu, Hongan Wang
Complex distributed real-time applications require complicated processing and sharing of an extensive amount of data under critical timing constraints. In this paper, we present a comprehensive overview of the Data Distribution Service standard (DDS) and describe its QoS (Quality of Service) features for developing real-time applications. Real-time ECA (RECA) rules are introduced to efficiently describe QoS policy in an active real-time database (ARTDB) named Agilor. And then we propose a novel QoS-Enable Real-Time Publish-Subscribe (QERTPS) service compatible to DDS for distributed real-time data acquisition. QERTPS could support several different QoS levels for various applications at the same time. Furthermore, QERTPS is implemented by object models and RECA rules in Agilor. To illustrate the benefits of QERTPS for real-time data acquisition, an example application is presented. Experimental evaluation shows that the proposed service provides a stable and timely service for providing different QoS levels.
{"title":"A Novel QoS-Enable Real-Time Publish-Subscribe Service","authors":"Xinjie Lv, Tian Yang, Zaifei Liao, Xin Li, Yongyan Wang, W. Liu, Hongan Wang","doi":"10.1109/ISPA.2008.61","DOIUrl":"https://doi.org/10.1109/ISPA.2008.61","url":null,"abstract":"Complex distributed real-time applications require complicated processing and sharing of an extensive amount of data under critical timing constraints. In this paper, we present a comprehensive overview of the Data Distribution Service standard (DDS) and describe its QoS (Quality of Service) features for developing real-time applications. Real-time ECA (RECA) rules are introduced to efficiently describe QoS policy in an active real-time database (ARTDB) named Agilor. And then we propose a novel QoS-Enable Real-Time Publish-Subscribe (QERTPS) service compatible to DDS for distributed real-time data acquisition. QERTPS could support several different QoS levels for various applications at the same time. Furthermore, QERTPS is implemented by object models and RECA rules in Agilor. To illustrate the benefits of QERTPS for real-time data acquisition, an example application is presented. Experimental evaluation shows that the proposed service provides a stable and timely service for providing different QoS levels.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"81 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134012491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wanida Putthividhya, Arka P. Ghosh, Wallapak Tavanapong
Modeling the available bandwidth of a path using a known stochastic process is one possible method for estimating future available bandwidth along the path without explicit support from network routers. Our two hypotheses for the stochastic process are as follows. First, an auto-regressive integrated moving-average process (ARIMA) is a suitable model for the available bandwidth over time of a path. Second, the available bandwidth over time of a path can be modeled as a self-similar process. We verify both hypotheses using R statistical software and available bandwidth data sets published by Stanford Linear Accelerator Center (SLAC). Our results indicate that the available bandwidth over time of an end-to-end path can be modeled as fractional Gaussian Noise (FGN) and seasonal fractional ARIMA (SFARIMA) processes. On the other hand, we found that an ARIMA process is not a good model for available bandwidth over time of an end-to-end path.
{"title":"Modeling of End-to-End Available Bandwidth in Wide Area Network","authors":"Wanida Putthividhya, Arka P. Ghosh, Wallapak Tavanapong","doi":"10.1109/ISPA.2008.56","DOIUrl":"https://doi.org/10.1109/ISPA.2008.56","url":null,"abstract":"Modeling the available bandwidth of a path using a known stochastic process is one possible method for estimating future available bandwidth along the path without explicit support from network routers. Our two hypotheses for the stochastic process are as follows. First, an auto-regressive integrated moving-average process (ARIMA) is a suitable model for the available bandwidth over time of a path. Second, the available bandwidth over time of a path can be modeled as a self-similar process. We verify both hypotheses using R statistical software and available bandwidth data sets published by Stanford Linear Accelerator Center (SLAC). Our results indicate that the available bandwidth over time of an end-to-end path can be modeled as fractional Gaussian Noise (FGN) and seasonal fractional ARIMA (SFARIMA) processes. On the other hand, we found that an ARIMA process is not a good model for available bandwidth over time of an end-to-end path.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115728295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kyriazis, K. Tserpes, George Kousiouris, A. Menychtas, G. Katsaros, T. Varvarigou
A constantly increasing number of applications from various scientific sectors are finding their way towards adopting grid technologies in order to take advantage of their capabilities: the advent of grid environments made feasible the solution of computational intensive problems in a reliable and cost-effective way. In this paper we present a grid-based approach for aggregation of data that are obtained from various sources (e.g. cameras, sensors) and their analysis with the use of genetic algorithms. By also taking into consideration general historical data and patient-specific medical information, we present the realization of the proposed approach with an application scenario for personalized healthcare and medicine.
{"title":"Data Aggregation and Analysis: A Grid-Based Approach for Medicine and Biology","authors":"D. Kyriazis, K. Tserpes, George Kousiouris, A. Menychtas, G. Katsaros, T. Varvarigou","doi":"10.1109/ISPA.2008.34","DOIUrl":"https://doi.org/10.1109/ISPA.2008.34","url":null,"abstract":"A constantly increasing number of applications from various scientific sectors are finding their way towards adopting grid technologies in order to take advantage of their capabilities: the advent of grid environments made feasible the solution of computational intensive problems in a reliable and cost-effective way. In this paper we present a grid-based approach for aggregation of data that are obtained from various sources (e.g. cameras, sensors) and their analysis with the use of genetic algorithms. By also taking into consideration general historical data and patient-specific medical information, we present the realization of the proposed approach with an application scenario for personalized healthcare and medicine.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124725627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a new model for information dissemination in communication network is presented. The model is defined on networks in which nodes are assigned some weights representing the internal delay they should pass before sending data to their neighbors. The new model, called weighted-vertex model, comes to have real world applications in parallel computation and satellite terrestrial networks. As a generalization of the classical model, optimum broadcasting in weighted-vertex model is NP_Hard. The problem remains NP_Hard in some classes of weighed-vertex graphs. We show existence of approximation algorithms for the broadcasting problem in weighted vertex model, as well as better approximations for specific subclasses of weighted graphs.
{"title":"Broadcasting in Weighted-Vertex Graphs","authors":"Hovhannes A. Harutyunyan, Shahin Kamali","doi":"10.1109/ISPA.2008.95","DOIUrl":"https://doi.org/10.1109/ISPA.2008.95","url":null,"abstract":"In this paper a new model for information dissemination in communication network is presented. The model is defined on networks in which nodes are assigned some weights representing the internal delay they should pass before sending data to their neighbors. The new model, called weighted-vertex model, comes to have real world applications in parallel computation and satellite terrestrial networks. As a generalization of the classical model, optimum broadcasting in weighted-vertex model is NP_Hard. The problem remains NP_Hard in some classes of weighed-vertex graphs. We show existence of approximation algorithms for the broadcasting problem in weighted vertex model, as well as better approximations for specific subclasses of weighted graphs.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121847075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In general, the cryptographic operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the cryptographic operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.
{"title":"Power-Efficient Architecture of Zigbee Security Processing","authors":"Jiho Kim, Jungyu Lee, Ohyoung Song","doi":"10.1109/ISPA.2008.113","DOIUrl":"https://doi.org/10.1109/ISPA.2008.113","url":null,"abstract":"In general, the cryptographic operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the cryptographic operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122812999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tim Süß, Daniel Huber, M. Fischer, C. Laroque, W. Dangelmaier
In this paper we present a system for the simultaneous visualization of several parallel executed simulation replications. By aggregating the scenes of multiple similar simulations into one single scene it is possible to make a visual statistical analysis of a set of discrete event simulations as well as to easily compare different system parameterizations. The aim of our system is to enhance the model analysis, verification and validation process in terms of speed and ease. The parallel execution of several simulations of complex models and the visualization of these cannot be done on one computer, thus a parallel approach is necessary. Our system uses a thin-client and multiple processors on a PC-cluster. The rendering and the simulation execution are done on processors of the cluster. The client is used only for the visualization of the images transmitted by the cluster and for user interaction.
{"title":"A System for Aggregated Visualization of Multiple Parallel Discrete Event Simulations","authors":"Tim Süß, Daniel Huber, M. Fischer, C. Laroque, W. Dangelmaier","doi":"10.1109/ISPA.2008.30","DOIUrl":"https://doi.org/10.1109/ISPA.2008.30","url":null,"abstract":"In this paper we present a system for the simultaneous visualization of several parallel executed simulation replications. By aggregating the scenes of multiple similar simulations into one single scene it is possible to make a visual statistical analysis of a set of discrete event simulations as well as to easily compare different system parameterizations. The aim of our system is to enhance the model analysis, verification and validation process in terms of speed and ease. The parallel execution of several simulations of complex models and the visualization of these cannot be done on one computer, thus a parallel approach is necessary. Our system uses a thin-client and multiple processors on a PC-cluster. The rendering and the simulation execution are done on processors of the cluster. The client is used only for the visualization of the images transmitted by the cluster and for user interaction.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125587768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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