The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.
{"title":"DMA Performance Analysis and Multi-core Memory Optimization for SWIM Benchmark on the Cell Processor","authors":"Y. Dou, Lin Deng, Jinhui Xu, Yi Zheng","doi":"10.1109/ISPA.2008.54","DOIUrl":"https://doi.org/10.1109/ISPA.2008.54","url":null,"abstract":"The Cell processor is a typical heterogeneous multi-core processor, which owns powerful computing capability. But we are facing the challenges of 'memory wall' in developing parallel applications, such as, limited capacity of local memory, limited memory bandwidth for multi-cores and the long latency for data communication. The DMA transfer mechanism is often used to hide the long latency and improve the effective usage of memory bandwidth. In the paper, we start with a series of DMA experimental tests in the context of the Cell processor architecture, and perform mathematical analysis to setup a unified formula on the average bandwidth of DMA by means of exponential fitting, which describes that SPE amount and DMA block size take main effects on DMA bandwidth in quantity. With the supports of the DMA performance formula, we perform 4 types of memory optimization in the process of parallelizing the SWIM benchmark program into a multi-core version. We take Sony PlayStation 3 (PS3) as our test-bed. For SWIM benchmark, with 6 SPE cores, we obtain over 13 times of speedup compared to single PPE, and 3.3 to 6.18 times to AMD and Intel CPU.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption has become one of the most critical concerns for processor design. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose simple models for analysing algorithms that reflect the energy-time trade-offs of CMOS circuits. Using these models, we derive lower bounds for the energy-constrained execution time of sorting, addition and multiplication, and we present algorithms that meet these bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth.
{"title":"Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds","authors":"B. Bingham, M. Greenstreet","doi":"10.1109/ISPA.2008.127","DOIUrl":"https://doi.org/10.1109/ISPA.2008.127","url":null,"abstract":"Power consumption has become one of the most critical concerns for processor design. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose simple models for analysing algorithms that reflect the energy-time trade-offs of CMOS circuits. Using these models, we derive lower bounds for the energy-constrained execution time of sorting, addition and multiplication, and we present algorithms that meet these bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. P. Freitas, A. Binotto, C. Pereira, A. Stork, Tony Larsson
Sensor networks are being applied in several emerging sophisticated applications due to the use of powerful and high-quality sensor nodes, such as radars and visible light cameras. However, these nodes need additional features to optimally benefit from heterogeneous modern computing platforms. Therefore, reconfigurable computing is a potential paradigm for those scenarios as it can provide flexibility to explore the computational resources on that kind of high performance computing system. This paper presents a reconfigurable sensor node allocation support, based on application requirements, provided by a middleware focused on heterogeneous sensor networks. In order to address this concern, an aspect-orientation paradigm and intelligent agents approach is proposed followed by an UAV case study.
{"title":"Dynamic Reconfigurable Task Schedule Support towards a Reflective Middleware for Sensor Network","authors":"E. P. Freitas, A. Binotto, C. Pereira, A. Stork, Tony Larsson","doi":"10.1109/ISPA.2008.70","DOIUrl":"https://doi.org/10.1109/ISPA.2008.70","url":null,"abstract":"Sensor networks are being applied in several emerging sophisticated applications due to the use of powerful and high-quality sensor nodes, such as radars and visible light cameras. However, these nodes need additional features to optimally benefit from heterogeneous modern computing platforms. Therefore, reconfigurable computing is a potential paradigm for those scenarios as it can provide flexibility to explore the computational resources on that kind of high performance computing system. This paper presents a reconfigurable sensor node allocation support, based on application requirements, provided by a middleware focused on heterogeneous sensor networks. In order to address this concern, an aspect-orientation paradigm and intelligent agents approach is proposed followed by an UAV case study.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116400141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xinjie Lv, Tian Yang, Zaifei Liao, Xin Li, Yongyan Wang, W. Liu, Hongan Wang
Complex distributed real-time applications require complicated processing and sharing of an extensive amount of data under critical timing constraints. In this paper, we present a comprehensive overview of the Data Distribution Service standard (DDS) and describe its QoS (Quality of Service) features for developing real-time applications. Real-time ECA (RECA) rules are introduced to efficiently describe QoS policy in an active real-time database (ARTDB) named Agilor. And then we propose a novel QoS-Enable Real-Time Publish-Subscribe (QERTPS) service compatible to DDS for distributed real-time data acquisition. QERTPS could support several different QoS levels for various applications at the same time. Furthermore, QERTPS is implemented by object models and RECA rules in Agilor. To illustrate the benefits of QERTPS for real-time data acquisition, an example application is presented. Experimental evaluation shows that the proposed service provides a stable and timely service for providing different QoS levels.
{"title":"A Novel QoS-Enable Real-Time Publish-Subscribe Service","authors":"Xinjie Lv, Tian Yang, Zaifei Liao, Xin Li, Yongyan Wang, W. Liu, Hongan Wang","doi":"10.1109/ISPA.2008.61","DOIUrl":"https://doi.org/10.1109/ISPA.2008.61","url":null,"abstract":"Complex distributed real-time applications require complicated processing and sharing of an extensive amount of data under critical timing constraints. In this paper, we present a comprehensive overview of the Data Distribution Service standard (DDS) and describe its QoS (Quality of Service) features for developing real-time applications. Real-time ECA (RECA) rules are introduced to efficiently describe QoS policy in an active real-time database (ARTDB) named Agilor. And then we propose a novel QoS-Enable Real-Time Publish-Subscribe (QERTPS) service compatible to DDS for distributed real-time data acquisition. QERTPS could support several different QoS levels for various applications at the same time. Furthermore, QERTPS is implemented by object models and RECA rules in Agilor. To illustrate the benefits of QERTPS for real-time data acquisition, an example application is presented. Experimental evaluation shows that the proposed service provides a stable and timely service for providing different QoS levels.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"81 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134012491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The simulation of the dynamics of the blood flow in the venous system of the lower limb is an important tool for supporting clinical research and for suggesting possible treatments for many diseases, e.g. for enhancing the surgical treatment of chronic venous insufficiency (CVI). Nevertheless the accuracy of the simulation of the blood flow is strictly related to the morphological data characterizing the investigated venous system. Although some of these data can be extracted from the observation of the real blood flow of a patient, e.g. through the acquisition of a set of images, the extraction of such values is often performed in a manual way, so the need for the automatic induction of parameters arises. The paper presents a software module that allows the semiautomatic acquisition of the morphological data of the venous system of a patient. The tool, developed as a plugin of the ImageJ imaging platform, receives in input a DICOM file containing the computerized tomography (CT) of the vessels network of the lower limb, and produces in a semi-automatic way a weighted graph of the network. This model can be used as the input for a subsequent simulation of the system.
{"title":"A Tool for the Semiautomatic Acquisition of the Morphological Data of Blood Vessel Networks","authors":"M. Cannataro, P. Guzzi, G. Tradigo, P. Veltri","doi":"10.1109/ISPA.2008.120","DOIUrl":"https://doi.org/10.1109/ISPA.2008.120","url":null,"abstract":"The simulation of the dynamics of the blood flow in the venous system of the lower limb is an important tool for supporting clinical research and for suggesting possible treatments for many diseases, e.g. for enhancing the surgical treatment of chronic venous insufficiency (CVI). Nevertheless the accuracy of the simulation of the blood flow is strictly related to the morphological data characterizing the investigated venous system. Although some of these data can be extracted from the observation of the real blood flow of a patient, e.g. through the acquisition of a set of images, the extraction of such values is often performed in a manual way, so the need for the automatic induction of parameters arises. The paper presents a software module that allows the semiautomatic acquisition of the morphological data of the venous system of a patient. The tool, developed as a plugin of the ImageJ imaging platform, receives in input a DICOM file containing the computerized tomography (CT) of the vessels network of the lower limb, and produces in a semi-automatic way a weighted graph of the network. This model can be used as the input for a subsequent simulation of the system.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Spin-lock is commonly used for process serialization, where it works well for multi processor systems. Under some conditions however, it may cause an unexpected increase of CPU overhead. To address this problem a simulator has been developed which evaluates various algorithms of the lock/unlock process to determine a method to minimize their affect on the stability and scalability of a system. This paper analyzes the effect of spin-lock, how CPU overhead changes as a function of traffic, by using the simulator. It demonstrates how multiple processors go into ldquobusy waitrdquo, consuming CPU time, and working for nothing, with only a few processors able to advance. The paper also shows how this problem can be solved by capped spin-lock where the spin is capped to a certain limit and a pause is inserted between the spins avoiding unnecessary consumption of CPU power and maintaining scalability over a number of processors.
{"title":"An Analysis of Exclusive Control Mechanisms","authors":"Kazuaki Masamoto, Takaichi Yoshida","doi":"10.1109/ISPA.2008.101","DOIUrl":"https://doi.org/10.1109/ISPA.2008.101","url":null,"abstract":"Spin-lock is commonly used for process serialization, where it works well for multi processor systems. Under some conditions however, it may cause an unexpected increase of CPU overhead. To address this problem a simulator has been developed which evaluates various algorithms of the lock/unlock process to determine a method to minimize their affect on the stability and scalability of a system. This paper analyzes the effect of spin-lock, how CPU overhead changes as a function of traffic, by using the simulator. It demonstrates how multiple processors go into ldquobusy waitrdquo, consuming CPU time, and working for nothing, with only a few processors able to advance. The paper also shows how this problem can be solved by capped spin-lock where the spin is capped to a certain limit and a pause is inserted between the spins avoiding unnecessary consumption of CPU power and maintaining scalability over a number of processors.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114946223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Kyriazis, K. Tserpes, George Kousiouris, A. Menychtas, G. Katsaros, T. Varvarigou
A constantly increasing number of applications from various scientific sectors are finding their way towards adopting grid technologies in order to take advantage of their capabilities: the advent of grid environments made feasible the solution of computational intensive problems in a reliable and cost-effective way. In this paper we present a grid-based approach for aggregation of data that are obtained from various sources (e.g. cameras, sensors) and their analysis with the use of genetic algorithms. By also taking into consideration general historical data and patient-specific medical information, we present the realization of the proposed approach with an application scenario for personalized healthcare and medicine.
{"title":"Data Aggregation and Analysis: A Grid-Based Approach for Medicine and Biology","authors":"D. Kyriazis, K. Tserpes, George Kousiouris, A. Menychtas, G. Katsaros, T. Varvarigou","doi":"10.1109/ISPA.2008.34","DOIUrl":"https://doi.org/10.1109/ISPA.2008.34","url":null,"abstract":"A constantly increasing number of applications from various scientific sectors are finding their way towards adopting grid technologies in order to take advantage of their capabilities: the advent of grid environments made feasible the solution of computational intensive problems in a reliable and cost-effective way. In this paper we present a grid-based approach for aggregation of data that are obtained from various sources (e.g. cameras, sensors) and their analysis with the use of genetic algorithms. By also taking into consideration general historical data and patient-specific medical information, we present the realization of the proposed approach with an application scenario for personalized healthcare and medicine.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124725627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, M. Mase, Y. Wada, H. Nakano, K. Kimura, H. Kasahara
Multicore processors have been adopted for consumer electronics like portable electronics, mobile phones, car navigation systems, digital TVs and games to obtain high performance with low power consumption. The OSCAR automatic parallelizing compiler has been developed to utilize these multicores easily. Also, a new consumer electronics multicore application program interface (API) to use the OSCAR compiler with native sequential compilers for various kinds of multicores from different vendors has been developed in NEDO (New Energy and Industrial Technology Development Organization) "Multicore Technology for Realtime Consumer Electronics" project with Japanese 6 IT companies. This paper evaluates the parallel processing performance of multimedia applications using this API by the OSCAR compiler on the FR1000 4 VLIW cores multicore processor developed by Fujitsu Ltd, and the RP1 4 SH-4A cores multicore processor jointly-developed by Renesas Technology Corp., Hitachi Ltd. and Waseda University. As the results, the parallel codes generated by the OSCAR compiler using the API give us 3.27 times speedup on average using 4 cores against 1 core on the FR1000 multicore, and 3.31 times speedup on average using 4 cores against 1 core on the RP1 multicore.
{"title":"Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API","authors":"Takamichi Miyamoto, Saori Asaka, Hiroki Mikami, M. Mase, Y. Wada, H. Nakano, K. Kimura, H. Kasahara","doi":"10.1109/ISPA.2008.58","DOIUrl":"https://doi.org/10.1109/ISPA.2008.58","url":null,"abstract":"Multicore processors have been adopted for consumer electronics like portable electronics, mobile phones, car navigation systems, digital TVs and games to obtain high performance with low power consumption. The OSCAR automatic parallelizing compiler has been developed to utilize these multicores easily. Also, a new consumer electronics multicore application program interface (API) to use the OSCAR compiler with native sequential compilers for various kinds of multicores from different vendors has been developed in NEDO (New Energy and Industrial Technology Development Organization) \"Multicore Technology for Realtime Consumer Electronics\" project with Japanese 6 IT companies. This paper evaluates the parallel processing performance of multimedia applications using this API by the OSCAR compiler on the FR1000 4 VLIW cores multicore processor developed by Fujitsu Ltd, and the RP1 4 SH-4A cores multicore processor jointly-developed by Renesas Technology Corp., Hitachi Ltd. and Waseda University. As the results, the parallel codes generated by the OSCAR compiler using the API give us 3.27 times speedup on average using 4 cores against 1 core on the FR1000 multicore, and 3.31 times speedup on average using 4 cores against 1 core on the RP1 multicore.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper a new model for information dissemination in communication network is presented. The model is defined on networks in which nodes are assigned some weights representing the internal delay they should pass before sending data to their neighbors. The new model, called weighted-vertex model, comes to have real world applications in parallel computation and satellite terrestrial networks. As a generalization of the classical model, optimum broadcasting in weighted-vertex model is NP_Hard. The problem remains NP_Hard in some classes of weighed-vertex graphs. We show existence of approximation algorithms for the broadcasting problem in weighted vertex model, as well as better approximations for specific subclasses of weighted graphs.
{"title":"Broadcasting in Weighted-Vertex Graphs","authors":"Hovhannes A. Harutyunyan, Shahin Kamali","doi":"10.1109/ISPA.2008.95","DOIUrl":"https://doi.org/10.1109/ISPA.2008.95","url":null,"abstract":"In this paper a new model for information dissemination in communication network is presented. The model is defined on networks in which nodes are assigned some weights representing the internal delay they should pass before sending data to their neighbors. The new model, called weighted-vertex model, comes to have real world applications in parallel computation and satellite terrestrial networks. As a generalization of the classical model, optimum broadcasting in weighted-vertex model is NP_Hard. The problem remains NP_Hard in some classes of weighed-vertex graphs. We show existence of approximation algorithms for the broadcasting problem in weighted vertex model, as well as better approximations for specific subclasses of weighted graphs.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121847075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In general, the cryptographic operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the cryptographic operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.
{"title":"Power-Efficient Architecture of Zigbee Security Processing","authors":"Jiho Kim, Jungyu Lee, Ohyoung Song","doi":"10.1109/ISPA.2008.113","DOIUrl":"https://doi.org/10.1109/ISPA.2008.113","url":null,"abstract":"In general, the cryptographic operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the cryptographic operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.","PeriodicalId":345341,"journal":{"name":"2008 IEEE International Symposium on Parallel and Distributed Processing with Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122812999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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