Pub Date : 2019-11-01DOI: 10.1109/witconece48374.2019.9092911
{"title":"[WITCON ECE 2019 Blank Page]","authors":"","doi":"10.1109/witconece48374.2019.9092911","DOIUrl":"https://doi.org/10.1109/witconece48374.2019.9092911","url":null,"abstract":"","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126321348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092939
S. Goutam, S. Unnikrishnan
The main contributions of the research paper are designing and implementation of an algorithm for handoff decision in WiFi coverage zone based on Fuzzy Logic. We have designed and implemented the handoff algorithm in WiFi coverage zone considering Free Space Propagation Model. We have considered Received Signal Strength, Channel Capacity, Network Load and User Velocity as the parameters in the algorithm. We have also studied the variation in point of handoff under the various conditions of Network Load, User Velocity and location of the access points.
{"title":"Handoff decision algorithm in WiFi zone using Fuzzy Logic","authors":"S. Goutam, S. Unnikrishnan","doi":"10.1109/WITCONECE48374.2019.9092939","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092939","url":null,"abstract":"The main contributions of the research paper are designing and implementation of an algorithm for handoff decision in WiFi coverage zone based on Fuzzy Logic. We have designed and implemented the handoff algorithm in WiFi coverage zone considering Free Space Propagation Model. We have considered Received Signal Strength, Channel Capacity, Network Load and User Velocity as the parameters in the algorithm. We have also studied the variation in point of handoff under the various conditions of Network Load, User Velocity and location of the access points.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126829819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092903
S. Pattar, L. N., Darshil Vala, V. Venkatesh, R. Buyya, V. R., S. Iyengar, L. Patnaik
With the deeper penetration of the Internet of Things (IoT) devices into the physical infrastructure and wider acceptance of IoT technologies by the community has created a tremendous opportunity for designers and developers to put forth applications that aim to improve the present state-of-the-art solutions. Location-based Service (LBS) provisioning is one such area where location data is utilized to offer user-centric services and thus improve personalized user experience. In this paper, we propose a search framework for the IoT ecosystem that offers location-aware services based on data messaging and aggregation techniques. We design a taxonomy for the classification of the IoT devices based on their mobility frequency and leverage it to design a priority scheme to address the co-located devices that offer similar services. Experimental results show that our proposed LBS Provisioning System is more effective in term of query resolution and storage requirements when compared to several existing works.
{"title":"Location-aware IoT Search Framework based on Data Messaging and Aggregation Techniques","authors":"S. Pattar, L. N., Darshil Vala, V. Venkatesh, R. Buyya, V. R., S. Iyengar, L. Patnaik","doi":"10.1109/WITCONECE48374.2019.9092903","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092903","url":null,"abstract":"With the deeper penetration of the Internet of Things (IoT) devices into the physical infrastructure and wider acceptance of IoT technologies by the community has created a tremendous opportunity for designers and developers to put forth applications that aim to improve the present state-of-the-art solutions. Location-based Service (LBS) provisioning is one such area where location data is utilized to offer user-centric services and thus improve personalized user experience. In this paper, we propose a search framework for the IoT ecosystem that offers location-aware services based on data messaging and aggregation techniques. We design a taxonomy for the classification of the IoT devices based on their mobility frequency and leverage it to design a priority scheme to address the co-located devices that offer similar services. Experimental results show that our proposed LBS Provisioning System is more effective in term of query resolution and storage requirements when compared to several existing works.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133551418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/witconece48374.2019.9092922
{"title":"WITCON ECE 2019 Author Index","authors":"","doi":"10.1109/witconece48374.2019.9092922","DOIUrl":"https://doi.org/10.1109/witconece48374.2019.9092922","url":null,"abstract":"","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120953726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092929
Avinash Sharma, Gopal Sharma, Arun kishor Johar, T. B. Kumar, D. Boolchandani
In this work design and analysis of Two Phase Frequency Detector (PFD) architectures have been carried out in SCL 180 nm CMOS technology. Performance of these PFD's are evaluated in terms of delay and power consumption. Supply voltage of 1.8 V is used to optimize the performance. Among the two designed PFD architectures, first PFD is designed using Multithreshold Complementary Oxide Semiconductor (MTCMOS) power gating technique and second is designed by utilizing feed forward reset PFD using external delay cell. First architecture has the advantage of reduced power consumption whereas second architecture is suitable for the design of high frequency and low jitter frequency synthesizers, as it offers very small dead zone. Simulation results display that feed forward PFD is free from dead zone but at the cost of increased complexity in terms of area and power consumption.
{"title":"Design, Analysis and Comparison of PFD Architectures for Fast Locking Frequency Synthesizer","authors":"Avinash Sharma, Gopal Sharma, Arun kishor Johar, T. B. Kumar, D. Boolchandani","doi":"10.1109/WITCONECE48374.2019.9092929","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092929","url":null,"abstract":"In this work design and analysis of Two Phase Frequency Detector (PFD) architectures have been carried out in SCL 180 nm CMOS technology. Performance of these PFD's are evaluated in terms of delay and power consumption. Supply voltage of 1.8 V is used to optimize the performance. Among the two designed PFD architectures, first PFD is designed using Multithreshold Complementary Oxide Semiconductor (MTCMOS) power gating technique and second is designed by utilizing feed forward reset PFD using external delay cell. First architecture has the advantage of reduced power consumption whereas second architecture is suitable for the design of high frequency and low jitter frequency synthesizers, as it offers very small dead zone. Simulation results display that feed forward PFD is free from dead zone but at the cost of increased complexity in terms of area and power consumption.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121032735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092930
Mitul Sen, Ardhendu Gatait, S. Ghosh, M. Chanda, Swarnil Roy, Papiya Debnath
A VERILOG A model of Bulk Current of Long- Channel Double-Gate Junctionless MOSFET is presented here. The basic physics of the model is briefly along with a simple flow chart. Proposed model data has been verified with the device models reported in the recent literatures. The model file is used to design and implement the Inverter, NAND/NOR circuits. Power dissipations and the delay of the double gate junctionless MOSFET based Inverter, NAND/NOR gates have been measured and compared with the conventional bulk MOSFET of similar dimensions. From the simulation data it is obvious that the junctionless MOSFET based digital logic circuits consume less power and higher speed compared to the conventional MOSFET based circuitry. The proposed model can be used to predict the power and delay of complex logic circuits based on the non-planner MOSFETs.
{"title":"Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application","authors":"Mitul Sen, Ardhendu Gatait, S. Ghosh, M. Chanda, Swarnil Roy, Papiya Debnath","doi":"10.1109/WITCONECE48374.2019.9092930","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092930","url":null,"abstract":"A VERILOG A model of Bulk Current of Long- Channel Double-Gate Junctionless MOSFET is presented here. The basic physics of the model is briefly along with a simple flow chart. Proposed model data has been verified with the device models reported in the recent literatures. The model file is used to design and implement the Inverter, NAND/NOR circuits. Power dissipations and the delay of the double gate junctionless MOSFET based Inverter, NAND/NOR gates have been measured and compared with the conventional bulk MOSFET of similar dimensions. From the simulation data it is obvious that the junctionless MOSFET based digital logic circuits consume less power and higher speed compared to the conventional MOSFET based circuitry. The proposed model can be used to predict the power and delay of complex logic circuits based on the non-planner MOSFETs.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092933
Kanchan Matiyali, S. Goel, Hitesh Joshi
This paper gives a detailed modelling of grid-tied PV system in which we presented a control strategy based on voltage oriented control scheme for grid-tied solar PV inverter which regulates point of common coupling (PCC) voltage and current considering near unity power factor. Hence only active power is controlled which is injected into the grid. For simulation purpose, a three-phase three-level (3L) diode clamped multilevel inverter (DCMLI) is used and a modulation technique having sinusoidal pulse width modulation (SPWM) is also formulated to provide gating pulse to the 3L inverter. The whole system is analysed based on inverter current, grid current and performance of inverter has been carried out. Effectiveness of the control system is studied and results are analyzed based on the total harmonic distortion (THD). The simulation work is carried out in Matlab/Simulink software.
{"title":"Voltage Oriented Control of Grid-tied Solar PV System","authors":"Kanchan Matiyali, S. Goel, Hitesh Joshi","doi":"10.1109/WITCONECE48374.2019.9092933","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092933","url":null,"abstract":"This paper gives a detailed modelling of grid-tied PV system in which we presented a control strategy based on voltage oriented control scheme for grid-tied solar PV inverter which regulates point of common coupling (PCC) voltage and current considering near unity power factor. Hence only active power is controlled which is injected into the grid. For simulation purpose, a three-phase three-level (3L) diode clamped multilevel inverter (DCMLI) is used and a modulation technique having sinusoidal pulse width modulation (SPWM) is also formulated to provide gating pulse to the 3L inverter. The whole system is analysed based on inverter current, grid current and performance of inverter has been carried out. Effectiveness of the control system is studied and results are analyzed based on the total harmonic distortion (THD). The simulation work is carried out in Matlab/Simulink software.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092908
M. Kashyap, Monika Gairola
Recently new innovation and advance technology has been introduced in the field of solar technology, which allows feasible access in the area of solar applications. Solar technology achieved these impressive targets in order to provide multiple applications that have been possible with the help of a production line through many PV industries. After getting such a response of the whole world towards renewable field it become necessary to enhance eco-friendly technology. Indian government also proclaim the target of 100 GW by 2022. Therefore, accomplishment of few new projects proved to be a great start but the challenges faced by PV industries is still concerning, which can lower down the speed towards target. And the main factor is its efficiency.
{"title":"Maximising Solar Cell Efficiency with PERC Technology","authors":"M. Kashyap, Monika Gairola","doi":"10.1109/WITCONECE48374.2019.9092908","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092908","url":null,"abstract":"Recently new innovation and advance technology has been introduced in the field of solar technology, which allows feasible access in the area of solar applications. Solar technology achieved these impressive targets in order to provide multiple applications that have been possible with the help of a production line through many PV industries. After getting such a response of the whole world towards renewable field it become necessary to enhance eco-friendly technology. Indian government also proclaim the target of 100 GW by 2022. Therefore, accomplishment of few new projects proved to be a great start but the challenges faced by PV industries is still concerning, which can lower down the speed towards target. And the main factor is its efficiency.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092895
Sandeepkumar Pandey, L. Garia
This paper presents the design of a compact multi-millimeter wave (MMW) antenna array. This is a 2-D Microstrip patch antenna which is designed by using collinear array concept for future 5G frequencies. By using edge feed mechanism providing better impedance matching between Microstrip line and patch antenna array. HFSS 18 is used to design and simulate this proposed antenna. The proposed antenna has dimensions of 19mm × 26mm(L × W). The substrate material used in proposed antenna is RT-duroid 5880 for achieving better gain and bandwidth. The substrate has dielectric constant = 2.2. This proposed 2-D antenna array is operating for four frequencies. These frequencies are 24.7GHz, 27.7GHz, 35.4GHz, 40.3GHz. This antenna has linear polarization over entire frequency spam. This proposed antenna offers high efficiency and high gain in all millimeter wave spectrum. The antenna's return loss is also very good. In E-plane and H-plane, the projected antenna has wider beam widths. Impedance bandwidth is also more from 34.18Ghz to 35.96Ghz. This projected antenna is useful for future 5G communication.
{"title":"Design of Millimeter-Wave Spectrum Microstrip Patch Antenna Array For 5G Wireless Systems","authors":"Sandeepkumar Pandey, L. Garia","doi":"10.1109/WITCONECE48374.2019.9092895","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092895","url":null,"abstract":"This paper presents the design of a compact multi-millimeter wave (MMW) antenna array. This is a 2-D Microstrip patch antenna which is designed by using collinear array concept for future 5G frequencies. By using edge feed mechanism providing better impedance matching between Microstrip line and patch antenna array. HFSS 18 is used to design and simulate this proposed antenna. The proposed antenna has dimensions of 19mm × 26mm(L × W). The substrate material used in proposed antenna is RT-duroid 5880 for achieving better gain and bandwidth. The substrate has dielectric constant = 2.2. This proposed 2-D antenna array is operating for four frequencies. These frequencies are 24.7GHz, 27.7GHz, 35.4GHz, 40.3GHz. This antenna has linear polarization over entire frequency spam. This proposed antenna offers high efficiency and high gain in all millimeter wave spectrum. The antenna's return loss is also very good. In E-plane and H-plane, the projected antenna has wider beam widths. Impedance bandwidth is also more from 34.18Ghz to 35.96Ghz. This projected antenna is useful for future 5G communication.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133975205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-11-01DOI: 10.1109/WITCONECE48374.2019.9092902
V. Narula, M. Agarwal
The correlation between silicon thickness and work function difference plays an important role to achieve best performance of field effect transistor. In this paper, a p-type double gate junctionless field effect transistor (DGJLT) performance is studied by varying the silicon thickness. Further, an interesting observation related to the correlation between silicon thickness and work function of the gate material is made. The best performance parameters of device are observed for lesser silicon thickness. However, on increasing the silicon thickness the deviceperformance can be maintained by tuning the work function of the gate material. The performance of the device is studied on the basis of different parameters like OFF current, ON current, ON/OFF current ratio, subthreshold slope (SS) and threshold voltage.
{"title":"Correlation betweenWork Function and Silicon Thickness of Double Gate Junctionless Field Effect Transistor","authors":"V. Narula, M. Agarwal","doi":"10.1109/WITCONECE48374.2019.9092902","DOIUrl":"https://doi.org/10.1109/WITCONECE48374.2019.9092902","url":null,"abstract":"The correlation between silicon thickness and work function difference plays an important role to achieve best performance of field effect transistor. In this paper, a p-type double gate junctionless field effect transistor (DGJLT) performance is studied by varying the silicon thickness. Further, an interesting observation related to the correlation between silicon thickness and work function of the gate material is made. The best performance parameters of device are observed for lesser silicon thickness. However, on increasing the silicon thickness the deviceperformance can be maintained by tuning the work function of the gate material. The performance of the device is studied on the basis of different parameters like OFF current, ON current, ON/OFF current ratio, subthreshold slope (SS) and threshold voltage.","PeriodicalId":350816,"journal":{"name":"2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125097056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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