Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570987
G. Lucovsky
Gate dielectrics comprised of nanocrystalline HfO2 in gate stacks with thin SiO2/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO2 and other transition metal elemental oxides are assigned to O-atom vacancies and possibly interstitials as well. These may be clustered at internal grain boundaries. Three potential engineering solutions for defect reduction are identified: i) deposition of ultra-thin, Lt 2 nm, HfO2 dielectric layers, in which grain boundary formation is suppressed by effectively eliminating inter-primitive unit cell-bonding interactions, ii) chemically phase-separated high HfO2 content silicates in which inter-primitive unit cell pi-bonding interactions are suppressed by nanocrystalline grain size limitations resulting from SiO2 inclusions and/or film thickness, and iii) non-crystalline Ti/Zr/Hf Si oxynitrides without grain boundary defects. However, each of these potential engineering solution dielectrics displays pre-existing as well as stress- induced defects.
{"title":"Narrowing the field of high-k gate dielectrics: intrinsic electronically-active bonding defects in nanocrystalline transition metal oxides","authors":"G. Lucovsky","doi":"10.1109/IWNC.2006.4570987","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570987","url":null,"abstract":"Gate dielectrics comprised of nanocrystalline HfO2 in gate stacks with thin SiO2/SiON interfacial transition regions display significant asymmetries with respect to trapping of Si substrate injected holes and electrons. Based on spectroscopic studies, and guided by ab initio theory, electron and hole traps in HfO2 and other transition metal elemental oxides are assigned to O-atom vacancies and possibly interstitials as well. These may be clustered at internal grain boundaries. Three potential engineering solutions for defect reduction are identified: i) deposition of ultra-thin, Lt 2 nm, HfO2 dielectric layers, in which grain boundary formation is suppressed by effectively eliminating inter-primitive unit cell-bonding interactions, ii) chemically phase-separated high HfO2 content silicates in which inter-primitive unit cell pi-bonding interactions are suppressed by nanocrystalline grain size limitations resulting from SiO2 inclusions and/or film thickness, and iii) non-crystalline Ti/Zr/Hf Si oxynitrides without grain boundary defects. However, each of these potential engineering solution dielectrics displays pre-existing as well as stress- induced defects.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"117 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133497393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570983
S.S. Chung
In this talk, an overview of the mobility enhancing techniques for high performance/low power CMOS technologies will be introduced first. Two categories for mobility enhancing schemes, channel induced strain using Si/SiGe, and hybrid-substrate engineering, with (100) and (110) orientations, will be discussed next. In terms of the device reliability, different mechanisms.. are responsible for these two different technologies. While we have paid much more attention on the performance of these technologies, the device reliability has not been taken care of in the past studies. As a consequence, this talk will address several examples of these mobility enhancing schemes and their impact on the device reliability for advanced CMOS technologies for 65 nm and beyond.
{"title":"Reliability issues for high performance nanoscale CMOS technologies with channel mobility enhancing schemes","authors":"S.S. Chung","doi":"10.1109/IWNC.2006.4570983","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570983","url":null,"abstract":"In this talk, an overview of the mobility enhancing techniques for high performance/low power CMOS technologies will be introduced first. Two categories for mobility enhancing schemes, channel induced strain using Si/SiGe, and hybrid-substrate engineering, with (100) and (110) orientations, will be discussed next. In terms of the device reliability, different mechanisms.. are responsible for these two different technologies. While we have paid much more attention on the performance of these technologies, the device reliability has not been taken care of in the past studies. As a consequence, this talk will address several examples of these mobility enhancing schemes and their impact on the device reliability for advanced CMOS technologies for 65 nm and beyond.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124066672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570997
K. Natori, T. Kurusu
New aspect of device characteristics emerging in nanostructured transistors are reviewed. Three topics are introduced and discussed. First, a new type of parasitic capacitance related to the charge layer thickness in capacitor electrode is discussed. Next, the quasi-ballistic operation of MOSFETs is analyzed in three aspects- one is the reflection-transmission formalism of MOS transport, another is an analysis of the device by Monte Carlo simulation, and the other discusses influence of device structure on its transport. In the last, we compare performance of a carbon nanotube FET to that of a silicon MOSFET.
{"title":"Novel aspects of nanoscale transistors","authors":"K. Natori, T. Kurusu","doi":"10.1109/IWNC.2006.4570997","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570997","url":null,"abstract":"New aspect of device characteristics emerging in nanostructured transistors are reviewed. Three topics are introduced and discussed. First, a new type of parasitic capacitance related to the charge layer thickness in capacitor electrode is discussed. Next, the quasi-ballistic operation of MOSFETs is analyzed in three aspects- one is the reflection-transmission formalism of MOS transport, another is an analysis of the device by Monte Carlo simulation, and the other discusses influence of device structure on its transport. In the last, we compare performance of a carbon nanotube FET to that of a silicon MOSFET.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124272709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570971
H. Iwai
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully introduce sub-10 nm CMOS LSIs into market, because the problems expected at this moment - such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we formed a leading research group for future ultra-low power nano-CMOS technology in 2003 - 2006, by the Special Coordination Funds for Promoting Science and Technology sponsored by Ministry of Education, Culture, Sports, Science and Technology, Japan, in order to conduct nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the group study was that, in the Nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Also, new physical analysis technique and physical model in order to predict and explain the atomic scale phenomena and properties at the new material interfaces are important. Unfortunately, there are no candidates among the so-called 'beyond CMOS' new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors - CMOS with FinFET, Nanowire FET, and even CNTFET - with 'More Moore' approach with combining that of 'More than Moore'.
近年来，CMOS的小型化进程在生产和研究层面都得到了极大的加快，甚至在一次会议上报道了5nm栅极长CMOS的晶体管运行情况。然而，即使在45纳米技术节点上，将小几何尺寸的mosfet实现到大规模集成电路中也存在许多严重的问题，并且我们是否能够成功地将10纳米以下的CMOS lsi引入市场仍然值得怀疑，因为目前预计的问题-例如离子/ off比，电流驱动，电气特性的变化，对产量，可靠性和制造成本的担忧。考虑到上述情况，我们于2003 - 2006年在日本文部科学省科技促进特别协调基金的资助下，成立了未来超低功耗纳米cmos技术的领先研究小组，提前开展纳米cmos研究，为未来可能出现的问题提供可能的解决方案。小组研究得出的结论是，在纳米cmos时代，需要积极引入新的材料、工艺、结构和操作理念来解决问题。此外，新的物理分析技术和物理模型对于预测和解释新材料界面的原子尺度现象和性质也很重要。不幸的是，在所谓的“超越CMOS”的新器件中，没有候选人，这被认为是在20年内真正取代可用于高度集成电路产品的CMOS晶体管。因此，我们的观点是，我们仍然需要继续以CMOS为基础的晶体管- CMOS与FinFET，纳米线FET，甚至CNTFET -与“More than Moore”相结合的“More Moore”方法。
{"title":"Recent status on Nano CMOS and future direction","authors":"H. Iwai","doi":"10.1109/IWNC.2006.4570971","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570971","url":null,"abstract":"Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length CMOS was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is still questionable if we can successfully introduce sub-10 nm CMOS LSIs into market, because the problems expected at this moment - such as Ion/Ioff ratio, current drive, variation in the electrical characteristics, concerns for the yield, reliability and manufacturing cost. Considering the above situation, we formed a leading research group for future ultra-low power nano-CMOS technology in 2003 - 2006, by the Special Coordination Funds for Promoting Science and Technology sponsored by Ministry of Education, Culture, Sports, Science and Technology, Japan, in order to conduct nano-CMOS studies in advance to provide possible solutions to the future expected problems. The conclusion obtained by the group study was that, in the Nano-CMOS era, aggressive introduction of new materials, processes, structures, and operation concepts is required to solve the problems. Also, new physical analysis technique and physical model in order to predict and explain the atomic scale phenomena and properties at the new material interfaces are important. Unfortunately, there are no candidates among the so-called 'beyond CMOS' new devices, which are believed to really replace CMOS transistors usable for the products of highly integrated circuits within 20 years. Thus, our opinion is that we need to still continue CMOS based transistors - CMOS with FinFET, Nanowire FET, and even CNTFET - with 'More Moore' approach with combining that of 'More than Moore'.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132938409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570981
N. Tanaka, J. Yamasaki, S. Inamoto, K. Saitoh
We have performed direct observations and elemental analyses of SiO2/Si(100) and La2O3/Si(100) by spherical aberration-corrected transmission electron microscopy (TEM) / scanning TEM (STEM) and ldquocombinatorial analysesrdquo by energy dispersive X-ray analysis (EDX) and electron energy loss spectroscopy (EELS). In SiO2/Si(100), the interfacial structures have been clearly observed without artificial image contrast. Atomic steps and defects on the Si(100) surfaces have been accurately identified. In La2O3/Si(100), epitaxial double layers have been observed after depositon at room temperature. These layers have been identified with lanthanum silicate and silicon oxide including a small amount of lanthanum atoms. Annealing at 500degC for 10 min have caused growth of both of the layers and exclusion of the lanthanum atoms from the silicon oxide layer. The growth mechanism of the layered structure and its influences on gate properties in MOSFETs have been discussed based on our experimental data.
{"title":"High-resolution TEM/STEM analysis of SiO2/Si(100) and La2O3/Si(100) interfaces","authors":"N. Tanaka, J. Yamasaki, S. Inamoto, K. Saitoh","doi":"10.1109/IWNC.2006.4570981","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570981","url":null,"abstract":"We have performed direct observations and elemental analyses of SiO2/Si(100) and La2O3/Si(100) by spherical aberration-corrected transmission electron microscopy (TEM) / scanning TEM (STEM) and ldquocombinatorial analysesrdquo by energy dispersive X-ray analysis (EDX) and electron energy loss spectroscopy (EELS). In SiO2/Si(100), the interfacial structures have been clearly observed without artificial image contrast. Atomic steps and defects on the Si(100) surfaces have been accurately identified. In La2O3/Si(100), epitaxial double layers have been observed after depositon at room temperature. These layers have been identified with lanthanum silicate and silicon oxide including a small amount of lanthanum atoms. Annealing at 500degC for 10 min have caused growth of both of the layers and exclusion of the lanthanum atoms from the silicon oxide layer. The growth mechanism of the layered structure and its influences on gate properties in MOSFETs have been discussed based on our experimental data.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115998811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570980
K. Kimura, Zhao Ming, K. Nakajima, M. Suzuki
A compact high-resolution RBS (HKBS) system, consisting of a simple magnetic spectrometer and a small accelerator, is used for Nano-CMOS applications. The HKBS system has several attractive features, e.g. capability of depth profiling with monolayer depth resolution, small footprint, reasonably short measuring time. Several examples of the applications are presented, which include observation of high-k/Si interface using grazing-angl-esputtering-assisted HKBS, hydrogen depth profiling in gate dielectric films, and observation of Si emission from the SiO2/Si interface during oxidation of HfO2/SiO2/Si(001). These examples show that HKBS is a powerful tool for Nano-CMOS applications.
{"title":"High-resolution Rutherford backscattering spectroscopy for Nano-CMOS applications","authors":"K. Kimura, Zhao Ming, K. Nakajima, M. Suzuki","doi":"10.1109/IWNC.2006.4570980","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570980","url":null,"abstract":"A compact high-resolution RBS (HKBS) system, consisting of a simple magnetic spectrometer and a small accelerator, is used for Nano-CMOS applications. The HKBS system has several attractive features, e.g. capability of depth profiling with monolayer depth resolution, small footprint, reasonably short measuring time. Several examples of the applications are presented, which include observation of high-k/Si interface using grazing-angl-esputtering-assisted HKBS, hydrogen depth profiling in gate dielectric films, and observation of Si emission from the SiO2/Si interface during oxidation of HfO2/SiO2/Si(001). These examples show that HKBS is a powerful tool for Nano-CMOS applications.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128353716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4571000
Y. Sasaki, C. Jin, B. Mizuno
Plasma doping technology has been expected to be an alternative method to beam line low energy ion implantation. First application will be shallow junction formation and doping for 3D structures. In this report, we tried to confirm the characterization methods for shallow junction, i.e., SIMS profiling for plasma doped layers shallower than 10 nm. This SIMS measurement method includes determining steepness of the profile tail. It is almost steeper than 2nm/decafe. Optical characteristics of the plasma doped layers were also investigated for optimizing optical annealing procedures.
{"title":"Characterization of plasma doped shallow junction","authors":"Y. Sasaki, C. Jin, B. Mizuno","doi":"10.1109/IWNC.2006.4571000","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4571000","url":null,"abstract":"Plasma doping technology has been expected to be an alternative method to beam line low energy ion implantation. First application will be shallow junction formation and doping for 3D structures. In this report, we tried to confirm the characterization methods for shallow junction, i.e., SIMS profiling for plasma doped layers shallower than 10 nm. This SIMS measurement method includes determining steepness of the profile tail. It is almost steeper than 2nm/decafe. Optical characteristics of the plasma doped layers were also investigated for optimizing optical annealing procedures.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117238282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570979
H. Nohira, T. Hattori
Hard and soft X-ray photoelectron spectroscopy study on the composition and the chemical structures of transition layers at La2O3/Si(100), Gd2O3/Si(100), Lu2O3/Si(100) and La2O3/Y2O3/Si(100) interfaces and their thermal stabilities are discussed. Soft X-ray photoelectron spectroscopy study on the distribution of nitrogen atomos in nearly 1-nm-thick oxynitride films and the chemical structures of the transition layer at SiO2/Si(100) interface are also discussed.
{"title":"Hard and soft X-ray excited photoelectron spectroscopy study on high-κ gate insulators","authors":"H. Nohira, T. Hattori","doi":"10.1109/IWNC.2006.4570979","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570979","url":null,"abstract":"Hard and soft X-ray photoelectron spectroscopy study on the composition and the chemical structures of transition layers at La<sub>2</sub>O<sub>3</sub>/Si(100), Gd<sub>2</sub>O<sub>3</sub>/Si(100), Lu<sub>2</sub>O<sub>3</sub>/Si(100) and La<sub>2</sub>O<sub>3</sub>/Y<sub>2</sub>O<sub>3</sub>/Si(100) interfaces and their thermal stabilities are discussed. Soft X-ray photoelectron spectroscopy study on the distribution of nitrogen atomos in nearly 1-nm-thick oxynitride films and the chemical structures of the transition layer at SiO<sub>2</sub>/Si(100) interface are also discussed.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122484690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570985
A. Seike, Itsutaku Sano, Keisaku Yamada, Iwao Ohdomari
Diffusion of phosphorus is studied by means of electrical measurement of the Si-wire devices and SIMS profiles of bulk SOI. The conductivity of Si-wire decreases as the thermal budget increases. The sample of 80 nm in the designed width (Wmask), of which the actual width after the oxidation is 57.4 nm, has higher conductivity, which is the factor of 3 to 4.5, with respect to the theoretical value of bulk Si. We assume that the stress applied from the peripheral SiO2 influence on the phosphorus diffusion in Si. Segregation of phosphorus ions at both cap-SiO2/Si(SOI) and Si(SOI)/SiO2(BOX) is recognized, however, no dependency of SIMS profiles on the thermal budget is confirmed. Dose loss of phosphorus due to the diffusion into the cap-SiO2 is about 1*1019 cm-3. The result of dependency of conductivity on the thermal budged doesnpsilat coincide with the data of SIMS profiles. This is because the SIMS profile of bulk sample doesnpsilat provide the lateral information nor reflect the effect of stress from the peripheral SiO2 film. Further investigation will be needed to reveal the relation between the size effect on the conductivity and the stress from the peripheral SiO2.
{"title":"Evaluation of phosphorus diffusion in the confined nano-wire under the influence of Si/SiO2 interface","authors":"A. Seike, Itsutaku Sano, Keisaku Yamada, Iwao Ohdomari","doi":"10.1109/IWNC.2006.4570985","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570985","url":null,"abstract":"Diffusion of phosphorus is studied by means of electrical measurement of the Si-wire devices and SIMS profiles of bulk SOI. The conductivity of Si-wire decreases as the thermal budget increases. The sample of 80 nm in the designed width (Wmask), of which the actual width after the oxidation is 57.4 nm, has higher conductivity, which is the factor of 3 to 4.5, with respect to the theoretical value of bulk Si. We assume that the stress applied from the peripheral SiO2 influence on the phosphorus diffusion in Si. Segregation of phosphorus ions at both cap-SiO2/Si(SOI) and Si(SOI)/SiO2(BOX) is recognized, however, no dependency of SIMS profiles on the thermal budget is confirmed. Dose loss of phosphorus due to the diffusion into the cap-SiO2 is about 1*1019 cm-3. The result of dependency of conductivity on the thermal budged doesnpsilat coincide with the data of SIMS profiles. This is because the SIMS profile of bulk sample doesnpsilat provide the lateral information nor reflect the effect of stress from the peripheral SiO2 film. Further investigation will be needed to reveal the relation between the size effect on the conductivity and the stress from the peripheral SiO2.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122642945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IWNC.2006.4570989
H. Przewlocki
A new approach to the photoelectric phenomena taking place in the MOS system at low electric fields in the dielectric has been developed and its basic features will be presented shortly. It allows calculation of some of the MOS structure characteristics and the good agreement between these calculated characteristics and the ones taken experimentally strongly supports the validity of the approach. Based on this new approach highly sensitive photoelectric measurement methods have been worked out. Principles underlying some of these methods, as well as experimental procedures applied will be presented. In particular, the importance will be underscored of the photoelectric measurement method of the effective contact potential difference (ECPD or phiMS) between the gate and the substrate of the MOS structure. This method is the most sensitive and most accurate of the existing methods of this parameter determination. In addition to their sensitivity and accuracy, photoelectric measurement methods allow determination of the local values of some of the MOS structure electrical parameters in the regions which are small in comparison with gate dimensions. This is done by illuminating small fragments of the gate area with a focused beam of UV radiation and measuring the resulting photocurrents in the external circuit. Scanning the gate area with such a UV radiation beam of small diameter allows determination of distributions of some of the electrical parameters over the gate area. In particular, the phiMS(x,y) distributions have been determined over gate areas of Al -SiO2-Si and poly-Si - SiO2 - Si structures. The differences between these distributions will be discussed. Using similar procedures, distributions of the barrier height local values at the gate-dielectric interface EBG(x,y) and at the semiconductor-dielectric interface EBS(x,y) can be determined. Such distributions will be demonstrated and compared with the phiMS(x,y) distribution determined for the same structure. Principles underlying possible further applications of the photoelectric measurement methods will also be discussed.
{"title":"New applications of internal photoemission to determine basic MOS system parameters","authors":"H. Przewlocki","doi":"10.1109/IWNC.2006.4570989","DOIUrl":"https://doi.org/10.1109/IWNC.2006.4570989","url":null,"abstract":"A new approach to the photoelectric phenomena taking place in the MOS system at low electric fields in the dielectric has been developed and its basic features will be presented shortly. It allows calculation of some of the MOS structure characteristics and the good agreement between these calculated characteristics and the ones taken experimentally strongly supports the validity of the approach. Based on this new approach highly sensitive photoelectric measurement methods have been worked out. Principles underlying some of these methods, as well as experimental procedures applied will be presented. In particular, the importance will be underscored of the photoelectric measurement method of the effective contact potential difference (ECPD or phiMS) between the gate and the substrate of the MOS structure. This method is the most sensitive and most accurate of the existing methods of this parameter determination. In addition to their sensitivity and accuracy, photoelectric measurement methods allow determination of the local values of some of the MOS structure electrical parameters in the regions which are small in comparison with gate dimensions. This is done by illuminating small fragments of the gate area with a focused beam of UV radiation and measuring the resulting photocurrents in the external circuit. Scanning the gate area with such a UV radiation beam of small diameter allows determination of distributions of some of the electrical parameters over the gate area. In particular, the phiMS(x,y) distributions have been determined over gate areas of Al -SiO2-Si and poly-Si - SiO2 - Si structures. The differences between these distributions will be discussed. Using similar procedures, distributions of the barrier height local values at the gate-dielectric interface EBG(x,y) and at the semiconductor-dielectric interface EBS(x,y) can be determined. Such distributions will be demonstrated and compared with the phiMS(x,y) distribution determined for the same structure. Principles underlying possible further applications of the photoelectric measurement methods will also be discussed.","PeriodicalId":356139,"journal":{"name":"2006 International Workshop on Nano CMOS","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116077846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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