Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95483
J. Baron, T.N. Rajashekhara
It is noted that the benefit of grading test vectors by fault simulation results in a savings of both time and money during the test stage for the detection of manufacturing defects. Accuracy, cost, and processing time are important features to be considered when evaluating fault simulation methods. It is suggested that the answer to which fault simulation solution is right needs to be evaluated on a case-by-case basis. It is shown that, although deterministic fault simulators are slow, they are and will be popular in the future because of their accuracy and hostability on general-purpose computers such as CAE (computer-aided engineering) workstations. Parallel processing methods lend themselves very nicely to fault simulation. With the widespread use of CAE workstations that are often connected together via a communication network, the hardware is already configured in a manner that is ready for parallel processing applications. An adequate trade-off between speed and accuracy can be obtained through the use of both a deterministic fault simulator and a statistical-based method.<>
{"title":"Fault simulation techniques for fabrication verification: a perspective","authors":"J. Baron, T.N. Rajashekhara","doi":"10.1109/STIER.1988.95483","DOIUrl":"https://doi.org/10.1109/STIER.1988.95483","url":null,"abstract":"It is noted that the benefit of grading test vectors by fault simulation results in a savings of both time and money during the test stage for the detection of manufacturing defects. Accuracy, cost, and processing time are important features to be considered when evaluating fault simulation methods. It is suggested that the answer to which fault simulation solution is right needs to be evaluated on a case-by-case basis. It is shown that, although deterministic fault simulators are slow, they are and will be popular in the future because of their accuracy and hostability on general-purpose computers such as CAE (computer-aided engineering) workstations. Parallel processing methods lend themselves very nicely to fault simulation. With the widespread use of CAE workstations that are often connected together via a communication network, the hardware is already configured in a manner that is ready for parallel processing applications. An adequate trade-off between speed and accuracy can be obtained through the use of both a deterministic fault simulator and a statistical-based method.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115618596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95461
H. N. Banerjee
The author provides an overview of the progress and the future trends of digital computer and microprocessor based hardware and software application in power system protection. It is noted that some of the most difficult aspects of providing the power system protection are reliability, accuracy, security, repeatability, reducing maintenance costs, reducing panel space requirements in control houses, and reducing engineering time to perform analytical studies. Particular attention is given to protection at extremely high voltage levels (230 kV and up). It is concluded that microprocessor-based protection design is a reliable and economical alternative to conventional designs. The protection engineering analysis and design programs are now mostly performed on PC or CAD/CAE (computer-aided design/engineering) computers.<>
{"title":"Computer application in power system protection","authors":"H. N. Banerjee","doi":"10.1109/STIER.1988.95461","DOIUrl":"https://doi.org/10.1109/STIER.1988.95461","url":null,"abstract":"The author provides an overview of the progress and the future trends of digital computer and microprocessor based hardware and software application in power system protection. It is noted that some of the most difficult aspects of providing the power system protection are reliability, accuracy, security, repeatability, reducing maintenance costs, reducing panel space requirements in control houses, and reducing engineering time to perform analytical studies. Particular attention is given to protection at extremely high voltage levels (230 kV and up). It is concluded that microprocessor-based protection design is a reliable and economical alternative to conventional designs. The protection engineering analysis and design programs are now mostly performed on PC or CAD/CAE (computer-aided design/engineering) computers.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127329877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95481
W. Kobrosly
The author describes the implementation of a task allocation algorithm for multiprocessing systems, providing a simulation package to allocate tasks among identical processors. The proposed model provides an optimal task-assignment strategy for distributed programs by using the graph theoretical approach proposed by W. Chu et al. (1980). This approach discusses the interconnections between the modules, which are distributed over many processors to take advantage of parallel processing. The simulation package that is used to simulate the task allocation is written in APL. It generates run-times, communication delays, and execution times for the tasks to be distributed. It then optimizes the system execution time and recommends a task allocation scheme based on these values. In addition, the author provides an allocation strategy based on simulation results. In particular, he focuses on the optimal values of the system run-time and communication delay, and subsequently the system execution time.<>
{"title":"Implementation of an optimal task allocation strategy","authors":"W. Kobrosly","doi":"10.1109/STIER.1988.95481","DOIUrl":"https://doi.org/10.1109/STIER.1988.95481","url":null,"abstract":"The author describes the implementation of a task allocation algorithm for multiprocessing systems, providing a simulation package to allocate tasks among identical processors. The proposed model provides an optimal task-assignment strategy for distributed programs by using the graph theoretical approach proposed by W. Chu et al. (1980). This approach discusses the interconnections between the modules, which are distributed over many processors to take advantage of parallel processing. The simulation package that is used to simulate the task allocation is written in APL. It generates run-times, communication delays, and execution times for the tasks to be distributed. It then optimizes the system execution time and recommends a task allocation scheme based on these values. In addition, the author provides an allocation strategy based on simulation results. In particular, he focuses on the optimal values of the system run-time and communication delay, and subsequently the system execution time.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116812826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95487
G. Randall, R. Sheftic, D. Spencer
The Manufacturing Automation Protocol (MAP) is a local area network designed specifically for the manufacturing plant environment. Writing from a user's perspective, the authors first review the reasons whey MAP was defined and how it has evolved to its existing state. Next, the components of MAP are discussed with an emphasis on the design of MAP application programs. This includes a discussion of the MAP network services and their associated user interfaces. Several examples of manufacturing system installation utilizing MAP are presented, and the characteristics of the applications are discussed. The authors conclude with a discussion of the latest MAP issues and their effect on MAP network implementations.<>
{"title":"The MAP evolution continues: a 1988 user perspective","authors":"G. Randall, R. Sheftic, D. Spencer","doi":"10.1109/STIER.1988.95487","DOIUrl":"https://doi.org/10.1109/STIER.1988.95487","url":null,"abstract":"The Manufacturing Automation Protocol (MAP) is a local area network designed specifically for the manufacturing plant environment. Writing from a user's perspective, the authors first review the reasons whey MAP was defined and how it has evolved to its existing state. Next, the components of MAP are discussed with an emphasis on the design of MAP application programs. This includes a discussion of the MAP network services and their associated user interfaces. Several examples of manufacturing system installation utilizing MAP are presented, and the characteristics of the applications are discussed. The authors conclude with a discussion of the latest MAP issues and their effect on MAP network implementations.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129894091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95472
N. G. Payne, P. Engel
It is noted that the relaxation stress greatly affects the reliability of electrical connectors. For proper functioning, adequate normal force must be maintained. Insulation displacement connectors (IDCs) promise increased economy over conventional electrical connectors; therefore, a high-reliability IDC has great potential in sophisticated office and business products. The authors describe an investigation of the stress relaxation of a few commercially available IDCs. Solid and stranded flat cables were studied experimentally and analytically. Dependences on temperature were also checked in 1000 h tests. Solid wires were found to yield less relaxation than stranded wires. While differences in performance due to size were slight, elevated temperature led to accelerated stress relaxation. When the connectors and wire combinations were used as tested, sufficient stress remained at end of life to maintain a gas-tight seal.<>
{"title":"Stress relaxation in an electrical connector","authors":"N. G. Payne, P. Engel","doi":"10.1109/STIER.1988.95472","DOIUrl":"https://doi.org/10.1109/STIER.1988.95472","url":null,"abstract":"It is noted that the relaxation stress greatly affects the reliability of electrical connectors. For proper functioning, adequate normal force must be maintained. Insulation displacement connectors (IDCs) promise increased economy over conventional electrical connectors; therefore, a high-reliability IDC has great potential in sophisticated office and business products. The authors describe an investigation of the stress relaxation of a few commercially available IDCs. Solid and stranded flat cables were studied experimentally and analytically. Dependences on temperature were also checked in 1000 h tests. Solid wires were found to yield less relaxation than stranded wires. While differences in performance due to size were slight, elevated temperature led to accelerated stress relaxation. When the connectors and wire combinations were used as tested, sufficient stress remained at end of life to maintain a gas-tight seal.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115095659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95475
N. Wu
A method of feedback controller design that results in maximal robustness in terms of closed-loop stability is proposed. The plants under consideration are linear with transmission delays. It is shown that, as long as a delay system can be approximated in the gap metric, the robust controller can be explicitly constructed to achieve the maximal stability robustness.<>
{"title":"Robust stabilization of time-delay systems","authors":"N. Wu","doi":"10.1109/STIER.1988.95475","DOIUrl":"https://doi.org/10.1109/STIER.1988.95475","url":null,"abstract":"A method of feedback controller design that results in maximal robustness in terms of closed-loop stability is proposed. The plants under consideration are linear with transmission delays. It is shown that, as long as a delay system can be approximated in the gap metric, the robust controller can be explicitly constructed to achieve the maximal stability robustness.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117060847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95478
T. Gaska
The author describes design issues in fault-tolerant vehicle management systems (VMS) for next-generation high-performance aircraft. Unstable aircraft require a highly reliable fault-tolerant computer to perform dynamic compensation of effector surface controls. Next-generation system requirements for system availability and performance will extend the role of flight criticality beyond the flight data sensors and actuation control functions. Additional control systems requiring a similar degree of fault tolerance include the primary and secondary electrical power systems, fuel management system, hydraulics control system, propulsion control system, and avionics cooling system. The incorporation of these additional control systems into the flight control system defines the vehicle management system of next-generation aircraft. In addition, the implementation of a VMS for the 1990s will incorporate state-of-the-art hardware technologies including fiber optics, high-speed local area networks, high-voltage application-specific integrated circuits, multiprocessing, smart sensors, liquid-cooled racks, and packaging for two-level maintenance. Software technology will include a multiprocessor ADA fault-tolerant executive, local area network distributed architecture synchronization and network management, and high coverage built-in-test to support two-level maintenance. Architectural and system technologies to be applied include channelized and self-monitored redundancy, integrated flight and propulsion control, centralized and distributed electric actuators, pooled processing centers, expert systems, and 270 V uninterruptible electrical systems. The goals and accomplishments of some VMS programs are summarized.<>
{"title":"Issues in the design of fault tolerant vehicle management systems for next generation unstable air vehicles","authors":"T. Gaska","doi":"10.1109/STIER.1988.95478","DOIUrl":"https://doi.org/10.1109/STIER.1988.95478","url":null,"abstract":"The author describes design issues in fault-tolerant vehicle management systems (VMS) for next-generation high-performance aircraft. Unstable aircraft require a highly reliable fault-tolerant computer to perform dynamic compensation of effector surface controls. Next-generation system requirements for system availability and performance will extend the role of flight criticality beyond the flight data sensors and actuation control functions. Additional control systems requiring a similar degree of fault tolerance include the primary and secondary electrical power systems, fuel management system, hydraulics control system, propulsion control system, and avionics cooling system. The incorporation of these additional control systems into the flight control system defines the vehicle management system of next-generation aircraft. In addition, the implementation of a VMS for the 1990s will incorporate state-of-the-art hardware technologies including fiber optics, high-speed local area networks, high-voltage application-specific integrated circuits, multiprocessing, smart sensors, liquid-cooled racks, and packaging for two-level maintenance. Software technology will include a multiprocessor ADA fault-tolerant executive, local area network distributed architecture synchronization and network management, and high coverage built-in-test to support two-level maintenance. Architectural and system technologies to be applied include channelized and self-monitored redundancy, integrated flight and propulsion control, centralized and distributed electric actuators, pooled processing centers, expert systems, and 270 V uninterruptible electrical systems. The goals and accomplishments of some VMS programs are summarized.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123479063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95468
S. Vassiliadis, M. Putrino, E. Schwarz
The authors introduce a unique formulation of multiplication for different notations with the unification of the multi-bit overlapped-scanning technique. Specifically, an algorithm for integer and fractional number representations is described for the two's-complement, sign-magnitude, one's-complement, and unsigned notations. It is indicated that a fractional, two's-complement multiplier with minor modifications can accommodate all the notations for integer and fractional representations. The minor modifications include the design of an (n+1)*(n+1) instead of an n*n multiplier with circuits for pre- and post-one's-complementation, and proper computation of the sign.<>
{"title":"Unified multi-bit overlapped-scanning multiplier algorithm","authors":"S. Vassiliadis, M. Putrino, E. Schwarz","doi":"10.1109/STIER.1988.95468","DOIUrl":"https://doi.org/10.1109/STIER.1988.95468","url":null,"abstract":"The authors introduce a unique formulation of multiplication for different notations with the unification of the multi-bit overlapped-scanning technique. Specifically, an algorithm for integer and fractional number representations is described for the two's-complement, sign-magnitude, one's-complement, and unsigned notations. It is indicated that a fractional, two's-complement multiplier with minor modifications can accommodate all the notations for integer and fractional representations. The minor modifications include the design of an (n+1)*(n+1) instead of an n*n multiplier with circuits for pre- and post-one's-complementation, and proper computation of the sign.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95469
M.R. Koplin, M. Randall
It is emphasized that computer performance is not achieved by accident but must be designed into the product from the beginning, and that this requires knowledge of the customer application. It is noted that this is a radical change from the approach of hardware design first, followed by the software being added on later, with performance measured last. The authors describe the need to predict performance and the significant elements of prediction. They also discuss the role of these predictions in the design process and the importance of system design. Performance checkpoints and validation are also discussed. The process described was used in the development of IBM S/370 mid-range processors.<>
{"title":"Performance by design: a management process","authors":"M.R. Koplin, M. Randall","doi":"10.1109/STIER.1988.95469","DOIUrl":"https://doi.org/10.1109/STIER.1988.95469","url":null,"abstract":"It is emphasized that computer performance is not achieved by accident but must be designed into the product from the beginning, and that this requires knowledge of the customer application. It is noted that this is a radical change from the approach of hardware design first, followed by the software being added on later, with performance measured last. The authors describe the need to predict performance and the significant elements of prediction. They also discuss the role of these predictions in the design process and the importance of system design. Performance checkpoints and validation are also discussed. The process described was used in the development of IBM S/370 mid-range processors.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116056007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95467
S. Kelkar, W. Moussa
Computer-based design tools for the electrical design of power converters have been developed for various topologies including push-pull, full-bridge, half-bridge, and others. The tools are intended to lay the foundation of the design through optimal values for key components. An example push-pull converter is used for illustration. Simulation tools play an important role in the design cycle; they are used to conform the design and predict performance under various conditions. A system-level simulation tool for power electronics has been developed, and its use is illustrated with reference to the push-pull converter. Measurements on the breadboarded converter are presented to confirm the usefulness of the design and simulation tools.<>
{"title":"CAD tools for electric design and simulation of push-pull topology power processors","authors":"S. Kelkar, W. Moussa","doi":"10.1109/STIER.1988.95467","DOIUrl":"https://doi.org/10.1109/STIER.1988.95467","url":null,"abstract":"Computer-based design tools for the electrical design of power converters have been developed for various topologies including push-pull, full-bridge, half-bridge, and others. The tools are intended to lay the foundation of the design through optimal values for key components. An example push-pull converter is used for illustration. Simulation tools play an important role in the design cycle; they are used to conform the design and predict performance under various conditions. A system-level simulation tool for power electronics has been developed, and its use is illustrated with reference to the push-pull converter. Measurements on the breadboarded converter are presented to confirm the usefulness of the design and simulation tools.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123631090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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