Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95474
W. Kobrosly, S. Vassiliadis
The authors survey several technical articles in the area of software testing and provide a cross section of software functional testing techniques. In particular, they focus on the systematic methodologies because such methodologies demonstrate the absence of unwanted erroneous functions and divide the testing effort into manageable pieces for automating the testing effort into manageable pieces for automating the testing process. The authors also discuss the empirical approach to assessing software validation methods and focus on the static and the dynamic techniques used to characterize this approach. Several techniques were found to be very useful for discovering different types of errors. For instance, the symbolic evaluation can be used to prove the correctness of a program without executing it by symbolically evaluating the sequence of the assignment statements occurring in a program path. Structured walkthroughs and design inspections result in substantial improvements in quality and productivity through the use of formal inspections of the design and the code.<>
{"title":"A survey of software functional testing techniques","authors":"W. Kobrosly, S. Vassiliadis","doi":"10.1109/STIER.1988.95474","DOIUrl":"https://doi.org/10.1109/STIER.1988.95474","url":null,"abstract":"The authors survey several technical articles in the area of software testing and provide a cross section of software functional testing techniques. In particular, they focus on the systematic methodologies because such methodologies demonstrate the absence of unwanted erroneous functions and divide the testing effort into manageable pieces for automating the testing effort into manageable pieces for automating the testing process. The authors also discuss the empirical approach to assessing software validation methods and focus on the static and the dynamic techniques used to characterize this approach. Several techniques were found to be very useful for discovering different types of errors. For instance, the symbolic evaluation can be used to prove the correctness of a program without executing it by symbolically evaluating the sequence of the assignment statements occurring in a program path. Structured walkthroughs and design inspections result in substantial improvements in quality and productivity through the use of formal inspections of the design and the code.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129949037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95476
J. Sklaroff, C. U. Smith
The authors present a methodology, a computer tool set, and writing guidelines that can assist the engineer in developing software specifications. The improved methodology addresses all types of specification inadequacies; the use of special tool sets addresses the technically deficient type of specification; and the adoption of writing guidelines addresses both technically deficient and poorly written types. The authors also discuss future challenges in making software specifications responsive to the needs of a rapidly changing avionics environment.<>
{"title":"Writing quality software specifications: the engineer's challenge","authors":"J. Sklaroff, C. U. Smith","doi":"10.1109/STIER.1988.95476","DOIUrl":"https://doi.org/10.1109/STIER.1988.95476","url":null,"abstract":"The authors present a methodology, a computer tool set, and writing guidelines that can assist the engineer in developing software specifications. The improved methodology addresses all types of specification inadequacies; the use of special tool sets addresses the technically deficient type of specification; and the adoption of writing guidelines addresses both technically deficient and poorly written types. The authors also discuss future challenges in making software specifications responsive to the needs of a rapidly changing avionics environment.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123440959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95473
F. Anderson
Application-specific integrated circuits (ASICs) are frequently utilized in applications demanding the highest circuit performance. Gate delays under 300 ps are now achievable using emitter coupled logic (ECL) and cascode current switch (CCS). However, as performance increases, so does the difficulty and cost of testing for quality parts. The design and operation of ECL and CCS and their sensitivities to chip failure mechanisms are discussed. By applying DC-level shifts to the internal signals, these faults can become testable. An approach to the design and test of these gates which enhances the testability of both AC and DC defects is given.<>
{"title":"Emitter coupled logic and cascode current switch testability and design for test","authors":"F. Anderson","doi":"10.1109/STIER.1988.95473","DOIUrl":"https://doi.org/10.1109/STIER.1988.95473","url":null,"abstract":"Application-specific integrated circuits (ASICs) are frequently utilized in applications demanding the highest circuit performance. Gate delays under 300 ps are now achievable using emitter coupled logic (ECL) and cascode current switch (CCS). However, as performance increases, so does the difficulty and cost of testing for quality parts. The design and operation of ECL and CCS and their sensitivities to chip failure mechanisms are discussed. By applying DC-level shifts to the internal signals, these faults can become testable. An approach to the design and test of these gates which enhances the testability of both AC and DC defects is given.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134010898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95482
Monish R. Chatterjee
It is shown that, in addition to its obvious merits in demonstrating and confirming theoretically tractable properties of electronic circuits and circuit models of physical systems, the SPICE simulation program can lead to unforeseen aspects of circuit behavior. Two specific examples are taken to illustrate this feature. In the first, it is shown how SPICE correctly predicted instability in a nonlinear capacitor model due to a physically incorrect choice of a parameter, later confirmed by a closer investigation of the theory. In the second, RF pulse experiments in an ensemble of nonlinear resonator circuits are shown to indicate temporal splitting of normal nonlinear echoes into multiple humps, which was not anticipated under approximate theory.<>
{"title":"On the usefulness of the SPICE simulation program in the prediction of anomalous behavior in complex nonlinear circuits","authors":"Monish R. Chatterjee","doi":"10.1109/STIER.1988.95482","DOIUrl":"https://doi.org/10.1109/STIER.1988.95482","url":null,"abstract":"It is shown that, in addition to its obvious merits in demonstrating and confirming theoretically tractable properties of electronic circuits and circuit models of physical systems, the SPICE simulation program can lead to unforeseen aspects of circuit behavior. Two specific examples are taken to illustrate this feature. In the first, it is shown how SPICE correctly predicted instability in a nonlinear capacitor model due to a physically incorrect choice of a parameter, later confirmed by a closer investigation of the theory. In the second, RF pulse experiments in an ensemble of nonlinear resonator circuits are shown to indicate temporal splitting of normal nonlinear echoes into multiple humps, which was not anticipated under approximate theory.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95488
T.W. Giambra
After providing an introduction to LANs (local area networks), the author reviews some performance considerations for the IBM token ring local area network (TRN). A system developed to tune a distributed processing TRN is discussed in detail. Particular attention is given to the development of a benchmark that could simulate the requirements of an expert system, while at the same time exercising the file I/O over the token ring network. A custom benchmark was developed which combines and translates into PROLOG three of Gabriel's LISP benchmarks: Browse, Fileprint, and Fileread. It is noted that the master/slave benchmark set-up used to measure remote response time could be implemented on almost any network with any LAN support software.<>
{"title":"Performance considerations for token ring networks","authors":"T.W. Giambra","doi":"10.1109/STIER.1988.95488","DOIUrl":"https://doi.org/10.1109/STIER.1988.95488","url":null,"abstract":"After providing an introduction to LANs (local area networks), the author reviews some performance considerations for the IBM token ring local area network (TRN). A system developed to tune a distributed processing TRN is discussed in detail. Particular attention is given to the development of a benchmark that could simulate the requirements of an expert system, while at the same time exercising the file I/O over the token ring network. A custom benchmark was developed which combines and translates into PROLOG three of Gabriel's LISP benchmarks: Browse, Fileprint, and Fileread. It is noted that the master/slave benchmark set-up used to measure remote response time could be implemented on almost any network with any LAN support software.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116814270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95466
S. Vassiliadis, E. Schwarz, M. Putrino
The authors consider 34 bit adder parity prediction schemes where the parity is predicted for either the 32 most significant or 32 least significant bits of the final 34 bit adder result, depending on the instruction being executed. Two parity prediction schemes are derived: one that considers the carries into the bytes and one that considers the carries into the nibbles. The two schemes save hardware and logic delay by grouping the adder bits common to both choices, rather than explicitly calculating the parity for the two separate 32 bit results and then choosing between them depending on the instruction performed. The hardware and its associated delay required to implement both parity predictors are of the same order of magnitude as for conventional 32 bit adder parity predictors.<>
{"title":"Parity predict for 34 bit adders with selection","authors":"S. Vassiliadis, E. Schwarz, M. Putrino","doi":"10.1109/STIER.1988.95466","DOIUrl":"https://doi.org/10.1109/STIER.1988.95466","url":null,"abstract":"The authors consider 34 bit adder parity prediction schemes where the parity is predicted for either the 32 most significant or 32 least significant bits of the final 34 bit adder result, depending on the instruction being executed. Two parity prediction schemes are derived: one that considers the carries into the bytes and one that considers the carries into the nibbles. The two schemes save hardware and logic delay by grouping the adder bits common to both choices, rather than explicitly calculating the parity for the two separate 32 bit results and then choosing between them depending on the instruction performed. The hardware and its associated delay required to implement both parity predictors are of the same order of magnitude as for conventional 32 bit adder parity predictors.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95485
C.J. Conant
The author describes an effort to produce an 8085-based standard (STD) bus system which includes a 16 bit analog (input/output) interface, a digital pulse-width-modulated output, and an RS232C interface to an IBM PC for downloading assembled programs. The main components of the system include an IBM PC, a STD bus card rack with +or-15 V supplies, and 8085 STD bus CPU card, a STD bus keyboard display card, a digital I/O card, a 16 bit analog I/O card, and a digital control card for the analog I/O. There are two possible methods of I/O in a digitally controlled second-order position control loop. The other method uses an analog-to-digital converter for the feedback inputs and a digital-to-analog converter for the servo amplifier output. Another method uses a digital encoder for the feedback inputs and a pulse-width-modulated signal for the servo amplifier output. The purpose of this design is to provide the basic hardware and software for an 8085-based digital control system which can be used for studying the differences between the above two methods of I/O.<>
{"title":"An 8085 based STD bus system for digital control applications","authors":"C.J. Conant","doi":"10.1109/STIER.1988.95485","DOIUrl":"https://doi.org/10.1109/STIER.1988.95485","url":null,"abstract":"The author describes an effort to produce an 8085-based standard (STD) bus system which includes a 16 bit analog (input/output) interface, a digital pulse-width-modulated output, and an RS232C interface to an IBM PC for downloading assembled programs. The main components of the system include an IBM PC, a STD bus card rack with +or-15 V supplies, and 8085 STD bus CPU card, a STD bus keyboard display card, a digital I/O card, a 16 bit analog I/O card, and a digital control card for the analog I/O. There are two possible methods of I/O in a digitally controlled second-order position control loop. The other method uses an analog-to-digital converter for the feedback inputs and a digital-to-analog converter for the servo amplifier output. Another method uses a digital encoder for the feedback inputs and a pulse-width-modulated signal for the servo amplifier output. The purpose of this design is to provide the basic hardware and software for an 8085-based digital control system which can be used for studying the differences between the above two methods of I/O.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128881422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95480
M. S. Robinson, T. Giambra
The authors describe the Distributed Intelligent Defense System (DIDS), a prototype research testbed targeted to a helicopter defense system developed under the IBM Systems Integration Division (SID) High Performance Inference Processing (HPIP) Independent Research and Development (IR&D) project. A brief overview of artificial intelligence (AI) in IBM's SID leading up to the development of the DIDS system is given, followed by a description of the development of the system itself. Performance measurement methodologies and results are then discussed. Several conclusions based on these results are given, along with plans for future system enhancements.<>
{"title":"The Distributed Intelligent Defense System","authors":"M. S. Robinson, T. Giambra","doi":"10.1109/STIER.1988.95480","DOIUrl":"https://doi.org/10.1109/STIER.1988.95480","url":null,"abstract":"The authors describe the Distributed Intelligent Defense System (DIDS), a prototype research testbed targeted to a helicopter defense system developed under the IBM Systems Integration Division (SID) High Performance Inference Processing (HPIP) Independent Research and Development (IR&D) project. A brief overview of artificial intelligence (AI) in IBM's SID leading up to the development of the DIDS system is given, followed by a description of the development of the system itself. Performance measurement methodologies and results are then discussed. Several conclusions based on these results are given, along with plans for future system enhancements.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114405388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-10-19DOI: 10.1109/STIER.1988.95459
Y. Zou, H. Ouibrahim
The authors consider the estimation of the directions of arrival in a multiple-source environment using a linear array of m sensors with d sources assumed to be in the far field and generating signals. A technique based on the moving window operator was proposed to estimate the locations of these sources. A Wiener filter preprocessing scheme to improve the estimates at low signal-to-noise ratios is described. On the basis of the knowledge of second-order statistics and the assumptions of stationary and time-invariant signals, the coefficients of the Wiener filter can be easily found. It is shown that the estimates of the directions of arrival are improved at low signal-to-noise ratios. Results of computer simulations carried out to evaluate the approach are also presented.<>
{"title":"Wiener filter processing for directions of arrival estimation using a moving window operator","authors":"Y. Zou, H. Ouibrahim","doi":"10.1109/STIER.1988.95459","DOIUrl":"https://doi.org/10.1109/STIER.1988.95459","url":null,"abstract":"The authors consider the estimation of the directions of arrival in a multiple-source environment using a linear array of m sensors with d sources assumed to be in the far field and generating signals. A technique based on the moving window operator was proposed to estimate the locations of these sources. A Wiener filter preprocessing scheme to improve the estimates at low signal-to-noise ratios is described. On the basis of the knowledge of second-order statistics and the assumptions of stationary and time-invariant signals, the coefficients of the Wiener filter can be easily found. It is shown that the estimates of the directions of arrival are improved at low signal-to-noise ratios. Results of computer simulations carried out to evaluate the approach are also presented.<<ETX>>","PeriodicalId":356590,"journal":{"name":"Proceedings of the IEEE Southern Tier Technical Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125359312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：