We use a Markov model to specify the behaviour of a protocol, and show an analysis of this model can generatea high-level design space that an engineer can explore. The behaviour that we study is the leakage power and the area complexity. The design space generated from the Markov model is shown to have high fidelity, which means it faithfully reflects the corresponding ‘implementation space’, and the lowest-power design will synthesise to the lowest-power implementation. In effect, the high-level Markov-based analysis we carry out allows low-level behaviour to be predicted, and this diminishes the need for extensive, time-consuming simulation. We also compute the theoretical lower and upper bounds of power, and in so doing, can determine how close our high-level designs are to being optimal. To test fidelity, we apply two different simulation tools, and measure the correlation between our high-level estimates and the results produced by simulation. In a case study, we predict which design of an AMBA protocol will consume least total power and cover least area.
{"title":"A Markov Model for Low-Power High-Fidelity Design-Space Exploration","authors":"Jing Cao, A. Nymeyer","doi":"10.1109/DSD.2010.47","DOIUrl":"https://doi.org/10.1109/DSD.2010.47","url":null,"abstract":"We use a Markov model to specify the behaviour of a protocol, and show an analysis of this model can generatea high-level design space that an engineer can explore. The behaviour that we study is the leakage power and the area complexity. The design space generated from the Markov model is shown to have high fidelity, which means it faithfully reflects the corresponding ‘implementation space’, and the lowest-power design will synthesise to the lowest-power implementation. In effect, the high-level Markov-based analysis we carry out allows low-level behaviour to be predicted, and this diminishes the need for extensive, time-consuming simulation. We also compute the theoretical lower and upper bounds of power, and in so doing, can determine how close our high-level designs are to being optimal. To test fidelity, we apply two different simulation tools, and measure the correlation between our high-level estimates and the results produced by simulation. In a case study, we predict which design of an AMBA protocol will consume least total power and cover least area.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126588791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper addresses the design-space exploration of network alternatives for complex distributed systems of embedded devices, e.g., for smart power grid or telecommunication services. While past research mainly provided efficient programming abstractions and HW/SW simulation tools, this work introduces the network perspective in the verification of different design solutions (e.g., different task decomposition and assignment to network nodes). To do that, network simulation capability has been added to the so-called Abstract Middleware Environment and its effectiveness has been shown experimentally through the design of a wireless sensor network application taken from a real-world case study.
{"title":"Exploration of Network Alternatives for Middleware-centric Embedded System Design","authors":"F. Fummi, G. Perbellini, D. Quaglia, R. Trenti","doi":"10.1109/DSD.2010.83","DOIUrl":"https://doi.org/10.1109/DSD.2010.83","url":null,"abstract":"The paper addresses the design-space exploration of network alternatives for complex distributed systems of embedded devices, e.g., for smart power grid or telecommunication services. While past research mainly provided efficient programming abstractions and HW/SW simulation tools, this work introduces the network perspective in the verification of different design solutions (e.g., different task decomposition and assignment to network nodes). To do that, network simulation capability has been added to the so-called Abstract Middleware Environment and its effectiveness has been shown experimentally through the design of a wireless sensor network application taken from a real-world case study.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127729596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault injection approach with 92% accuracy. This makes the proposed approach applicable to industrial-scale circuits.
{"title":"A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits","authors":"M. Fazeli, S. Miremadi, H. Asadi, M. Tahoori","doi":"10.1109/DSD.2010.74","DOIUrl":"https://doi.org/10.1109/DSD.2010.74","url":null,"abstract":"In this paper, we propose a very fast analytical approach to measure the overall circuit Soft Error Rate (SER) and to identify the most vulnerable gates and flip-flops. In the proposed approach, we first compute the error propagation probability from an error site to primary outputs as well as system bistables. Then, we perform a multi-cycle error propagation analysis in the sequential circuit. The results show that the proposed approach is four to five orders of magnitude faster than the Monte Carlo (MC) simulation-based fault injection approach with 92% accuracy. This makes the proposed approach applicable to industrial-scale circuits.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115212855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13μm CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and very suitable for practical applications because of its balanced performance and hardware-complexity; moreover it has the flexibility to be expanded into an eight-nodes-per-cycle version in order to double the throughput.
{"title":"A Novel VLSI Architecture of Fixed-Complexity Sphere Decoder","authors":"Bin Wu, G. Masera","doi":"10.1109/DSD.2010.10","DOIUrl":"https://doi.org/10.1109/DSD.2010.10","url":null,"abstract":"Fixed-complexity Sphere Decoder (FSD) is a recently proposed technique for Multiple-Input Multiple-Output (MIMO) detection. It has several outstanding features such as constant throughput and large potential parallelism, which makes it suitable for efficient VLSI implementation. However, to our best knowledge, no VLSI implementation of FSD has been reported in the literature, although some FPGA prototypes of FSD with pipeline architecture have been developed. These solutions achieve very high throughput but at very high cost of hardware resources, making them impractical in real applications. In this paper, we present a novel four-nodes-per-cycle parallel architecture of FSD, with a breadth-first processing that allows for short critical path. The implementation achieves a throughput of 213.3 Mbps at 400 MHz clock frequency, at a cost of 0.18 mm2 Silicon area on 0.13μm CMOS technology. The proposed solution is much more economical compared with the existing FPGA implementations, and very suitable for practical applications because of its balanced performance and hardware-complexity; moreover it has the flexibility to be expanded into an eight-nodes-per-cycle version in order to double the throughput.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122930698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.
{"title":"On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism","authors":"Xiao Zhang, H. Kerkhoff, B. Vermeulen","doi":"10.1109/DSD.2010.16","DOIUrl":"https://doi.org/10.1109/DSD.2010.16","url":null,"abstract":"Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since the scan-based test is performed on-chip via the NoC at application run-time, it needs to share the NoC bandwidth with other applications. Instead of reserving sufficient NoC bandwidth for the test, the authors propose a novel way to carry out scan-based tests by dynamically pausing and resuming the test data flow to accommodate the fluctuating communication bandwidth available on the NoC. The test stimuli application and test response collection processes are decoupled to meet the global timing constraint. The many-core processor, IIP and the NoC have been implemented in synthesizable VHDL. Simulation results show the correct application of standard structural test patterns to the processing tiles and the test response collection at run-time using the proposed approach.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117030385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stefan Frehse, G. Fey, André Sülflow, R. Drechsler
Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Automated support is required to analyze the fault tolerance of circuits. In this paper, Robu Check is presented - a design tool to analyze the fault tolerance of digital circuits. Engines based on simulation and formal methods are integrated to identify components that require additional fault protection. Consequently, an overall estimation of fault tolerance of the circuit is determined.
{"title":"RobuCheck: A Robustness Checker for Digital Circuits","authors":"Stefan Frehse, G. Fey, André Sülflow, R. Drechsler","doi":"10.1145/1772630.1772641","DOIUrl":"https://doi.org/10.1145/1772630.1772641","url":null,"abstract":"Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Automated support is required to analyze the fault tolerance of circuits. In this paper, Robu Check is presented - a design tool to analyze the fault tolerance of digital circuits. Engines based on simulation and formal methods are integrated to identify components that require additional fault protection. Consequently, an overall estimation of fault tolerance of the circuit is determined.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115297539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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