Continuous advances in transistor manufacturing have enabled technology scaling along the years, sustaining Moore's law. As transistors sizes rapidly shrink, and voltage scales, the amount of charge in a node also rapidly decreases. A particle hitting the core will probably cause a transient fault to spam over several clock cycles. In this scenario, embedded systems using state-of-the-art technologies will face the challenge of operating in an environment susceptible to multiple errors, but with restricted resources available to deploy fault-tolerance, as these techniques severely increase power consumption. One possible solution to this problem is the adoption of software based fault-tolerance at the system level, aiming at reduced energy levels to ensure reliability and low energy dissipation. In this paper, we claim the detection and correction of errors on generic data structures at system level by using matrices to encode any program and algorithm. With such encoding, it is possible to employ established techniques of detection and correction of errors occurring in matrices, running with inexpressive overhead of power and energy. We evaluated this proposal using two case studies significant for the embedded system domain. Using the proposed approach, we observed in some cases an overhead of only 5% in performance and 8% in program size.
{"title":"System Level Hardening by Computing with Matrices","authors":"R. Ferreira, Álvaro Freitas Moreira, L. Carro","doi":"10.1109/DSD.2010.8","DOIUrl":"https://doi.org/10.1109/DSD.2010.8","url":null,"abstract":"Continuous advances in transistor manufacturing have enabled technology scaling along the years, sustaining Moore's law. As transistors sizes rapidly shrink, and voltage scales, the amount of charge in a node also rapidly decreases. A particle hitting the core will probably cause a transient fault to spam over several clock cycles. In this scenario, embedded systems using state-of-the-art technologies will face the challenge of operating in an environment susceptible to multiple errors, but with restricted resources available to deploy fault-tolerance, as these techniques severely increase power consumption. One possible solution to this problem is the adoption of software based fault-tolerance at the system level, aiming at reduced energy levels to ensure reliability and low energy dissipation. In this paper, we claim the detection and correction of errors on generic data structures at system level by using matrices to encode any program and algorithm. With such encoding, it is possible to employ established techniques of detection and correction of errors occurring in matrices, running with inexpressive overhead of power and energy. We evaluated this proposal using two case studies significant for the embedded system domain. Using the proposed approach, we observed in some cases an overhead of only 5% in performance and 8% in program size.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114952292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic control flow checking (DCFC) technique for high reliable computer systems. The DCFC technique dynamically generates reference signatures as well as runtime signatures during executing a program. The dynamic generation of reference and runtime signatures contributes to saving program or data memory space that stores the signatures. Our DCFC technique stores signatures in a signature table unlike the conventional static control flow checking techniques. Our experiments showed that our DCFC technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.
{"title":"Dynamic Control Flow Checking Technique for Reliable Microprocessors","authors":"M. Sugihara","doi":"10.1109/DSD.2010.81","DOIUrl":"https://doi.org/10.1109/DSD.2010.81","url":null,"abstract":"Reliability issues such as a soft error and NBTI (negative bias temperature instability) have become a matter of concern as integrated circuits continue to shrink. It is getting more and more important to take reliability requirements into account even for consumer products. This paper presents a dynamic control flow checking (DCFC) technique for high reliable computer systems. The DCFC technique dynamically generates reference signatures as well as runtime signatures during executing a program. The dynamic generation of reference and runtime signatures contributes to saving program or data memory space that stores the signatures. Our DCFC technique stores signatures in a signature table unlike the conventional static control flow checking techniques. Our experiments showed that our DCFC technique protected 1.4-100.0% of executed instructions depending on the size of signature tables.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"9 44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vector Median Filters (VMFs) are used in many image and video processing applications. Recently, they are used for Frame Rate Up-Conversion (FRC). However, they are difficult to implement in real-time because of their high computational complexity. Therefore, in this paper, we propose several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the motion vector field. In addition, we designed and implemented an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field on a low cost Xilinx XC3S400A-5 FPGA. The FPGA implementation can work at 145 MHz and it can process more than 94 high definition frames per second.
{"title":"Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation","authors":"Ozgur Tasdizen, Ilker Hamzaoglu","doi":"10.1109/DSD.2010.102","DOIUrl":"https://doi.org/10.1109/DSD.2010.102","url":null,"abstract":"Vector Median Filters (VMFs) are used in many image and video processing applications. Recently, they are used for Frame Rate Up-Conversion (FRC). However, they are difficult to implement in real-time because of their high computational complexity. Therefore, in this paper, we propose several techniques to reduce the computational complexity of VMFs by using data reuse methodology and by exploiting the spatial correlations in the motion vector field. In addition, we designed and implemented an efficient VMF hardware including the computation reduction techniques exploiting the spatial correlations in the motion vector field on a low cost Xilinx XC3S400A-5 FPGA. The FPGA implementation can work at 145 MHz and it can process more than 94 high definition frames per second.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128679321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The host-SIMD style heterogeneous multi-processor architecture offers high computing performance and user friendly programmability. It explores both task level parallelism and data level parallelism by the on-chip multiple SIMD coprocessors. For embedded DSP applications with predictable computing feature, this architecture can be further optimized for performance, implementation cost and power consumption. The optimization could be done by improving the SIMD processing efficiency and reducing redundant memory accesses and data shuffle operations. This paper introduces one effective approach by designing a software programmable multi-bank memory system for SIMD processors. Both the hardware architecture and software programming model are described in this paper, with an implementation example of the BLAS syrk routine. The proposed memory system offers high SIMD data access flexibility by using lookup table based address generators, and applying data permutations on both DMA controller interface and SIMD data access. The evaluation results show that the SIMD processor with this memory system can achieve high execution efficiency, with only 10% to 30% overhead. The proposed memory system also saves the implementation cost on SIMD local registers, in our system, each SIMD core has only 8 128-bit vector registers.
{"title":"Software Programmable Data Allocation in Multi-bank Memory of SIMD Processors","authors":"Jian Wang, Joar Sohl, Olof Kraigher, Dake Liu","doi":"10.1109/DSD.2010.26","DOIUrl":"https://doi.org/10.1109/DSD.2010.26","url":null,"abstract":"The host-SIMD style heterogeneous multi-processor architecture offers high computing performance and user friendly programmability. It explores both task level parallelism and data level parallelism by the on-chip multiple SIMD coprocessors. For embedded DSP applications with predictable computing feature, this architecture can be further optimized for performance, implementation cost and power consumption. The optimization could be done by improving the SIMD processing efficiency and reducing redundant memory accesses and data shuffle operations. This paper introduces one effective approach by designing a software programmable multi-bank memory system for SIMD processors. Both the hardware architecture and software programming model are described in this paper, with an implementation example of the BLAS syrk routine. The proposed memory system offers high SIMD data access flexibility by using lookup table based address generators, and applying data permutations on both DMA controller interface and SIMD data access. The evaluation results show that the SIMD processor with this memory system can achieve high execution efficiency, with only 10% to 30% overhead. The proposed memory system also saves the implementation cost on SIMD local registers, in our system, each SIMD core has only 8 128-bit vector registers.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128788854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A promising approach to high-level design is to start initially with an obvious but possibly inefficient design, and apply multiple transformations to meet design goals. Many hardware compilation tools support a fixed recipe of applying design transformations, but designers have few options to adapt the recipe without re-writing the tools themselves. In addition, complex transformations based on linear programming and geometric programming are often not included. This paper proposes anew approach that enables designers to customize the composition and parameterization of different types of design transformations in a unified framework, using a high-level language to control a transformation engine to automate the application of design transformations. Our approach is implemented by a tool based on the Python language and the ROSE compiler framework, which supports both syntax-directed transformations such as loop coalescing, and goal-directed transformations such as geometric programming. We illustrate how customizing the composition and parameterization of design transformations can lead to designs with different trade-offs in performance, resource usage, and energy efficiency. We evaluate our approach on benchmarks including matrix multiplication, Monte Carlo simulation of Asian options, edge detection, FIR filtering, and motion estimation.
{"title":"Customizable Composition and Parameterization of Hardware Design Transformations","authors":"T. Todman, Qiang Liu, W. Luk, G. Constantinides","doi":"10.1109/DSD.2010.78","DOIUrl":"https://doi.org/10.1109/DSD.2010.78","url":null,"abstract":"A promising approach to high-level design is to start initially with an obvious but possibly inefficient design, and apply multiple transformations to meet design goals. Many hardware compilation tools support a fixed recipe of applying design transformations, but designers have few options to adapt the recipe without re-writing the tools themselves. In addition, complex transformations based on linear programming and geometric programming are often not included. This paper proposes anew approach that enables designers to customize the composition and parameterization of different types of design transformations in a unified framework, using a high-level language to control a transformation engine to automate the application of design transformations. Our approach is implemented by a tool based on the Python language and the ROSE compiler framework, which supports both syntax-directed transformations such as loop coalescing, and goal-directed transformations such as geometric programming. We illustrate how customizing the composition and parameterization of design transformations can lead to designs with different trade-offs in performance, resource usage, and energy efficiency. We evaluate our approach on benchmarks including matrix multiplication, Monte Carlo simulation of Asian options, edge detection, FIR filtering, and motion estimation.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124627724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Storage arrays are widely used in integrated biosensor systems to store detected signals before and after they are processed. As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power consumption for storage arrays in integrated biosensor systems should be kept low, whereas the speed requirement is usually not high such that state-of-the-art IC technology is not usually needed. This paper presents the results of our investigation of designing low power memory structures in sub 1-V operation with high reliability for biosensor systems. Rather than using the state-of-the-art 45nm/32nm technology, 0.18 um CMOS technology is used for the design to keep the overall cost down while achieving read and write performance of 200MHz cycle rate. The results show that the use of body back bias in systems with low supply voltage can improve memory's static noise margin (SNM) and memory write performance by as much as 25%.
存储阵列广泛应用于集成生物传感器系统中，用于存储处理前后的检测信号。由于集成生物传感器系统通常需要非常低的功耗来延长电池寿命并保持低成本，因此集成生物传感器系统中存储阵列的功耗应保持在低水平，而速度要求通常不高，因此通常不需要最先进的IC技术。本文介绍了我们为生物传感器系统设计低功耗、低电压、高可靠性的存储结构的研究结果。该设计采用了0.18 um CMOS技术，而不是使用最先进的45nm/32nm技术，以降低总体成本，同时实现200MHz周期速率的读写性能。结果表明，在低电源电压系统中使用体背偏置可使存储器的静态噪声裕度(SNM)和存储器写入性能提高多达25%。
{"title":"On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications","authors":"Allen Chen, Ryan Hoppal, Tom Chen","doi":"10.1109/DSD.2010.113","DOIUrl":"https://doi.org/10.1109/DSD.2010.113","url":null,"abstract":"Storage arrays are widely used in integrated biosensor systems to store detected signals before and after they are processed. As integrated biosensor systems often require very low power consumption to extend battery life and to maintain low cost, power consumption for storage arrays in integrated biosensor systems should be kept low, whereas the speed requirement is usually not high such that state-of-the-art IC technology is not usually needed. This paper presents the results of our investigation of designing low power memory structures in sub 1-V operation with high reliability for biosensor systems. Rather than using the state-of-the-art 45nm/32nm technology, 0.18 um CMOS technology is used for the design to keep the overall cost down while achieving read and write performance of 200MHz cycle rate. The results show that the use of body back bias in systems with low supply voltage can improve memory's static noise margin (SNM) and memory write performance by as much as 25%.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127450535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Increasing diversity in packet-processing applications and rapid increases in channel bandwidth lead to greater complexity in communication protocols. These factors result in larger computational loads for packet-processing engines that introduce high performance microprocessor designs as an important solution. This paper presents an exhaustive simulation for exploring the performance of instruction-level parallel super scalar processors executing packet-processing applications. Based on the simulation results, a design space exploration has been used to derive performance-efficient application-specific super scalar processor architecture based on MIPS instruction set architecture. Simple Scalar architecture toolset has been used for design space exploration and network applications have been investigated to guide the architecture exploration. The optimizations achieve up to 80% improvement in performance for representative packet-processing applications.
{"title":"Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications","authors":"M. Salehi, H. Dorosti, S. M. Fakhraie","doi":"10.1109/DSD.2010.94","DOIUrl":"https://doi.org/10.1109/DSD.2010.94","url":null,"abstract":"Increasing diversity in packet-processing applications and rapid increases in channel bandwidth lead to greater complexity in communication protocols. These factors result in larger computational loads for packet-processing engines that introduce high performance microprocessor designs as an important solution. This paper presents an exhaustive simulation for exploring the performance of instruction-level parallel super scalar processors executing packet-processing applications. Based on the simulation results, a design space exploration has been used to derive performance-efficient application-specific super scalar processor architecture based on MIPS instruction set architecture. Simple Scalar architecture toolset has been used for design space exploration and network applications have been investigated to guide the architecture exploration. The optimizations achieve up to 80% improvement in performance for representative packet-processing applications.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130704165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tingcong Ye, D. Vasudevan, Jiaoyan Chen, E. Popovici, M. Schellekens
In this paper a new static average case dynamic power estimation technique is introduced based on the property of randomness preservation for digital circuits. The proposed technique is validated by estimating the average case power for a block cipher, DES with a lower estimation error percentage of 0.9481 % and lesser simulation time with a pattern reduction of (2^n x 2^n!)-(2^n x 2^n x 2) for n bit design. The same technique can be extended to any block cipher, including the AES and IDEA-NXT.
基于数字电路的随机性保持特性，提出了一种新的静态平均情况动态功率估计技术。通过估计分组密码的平均case功率来验证所提出的技术，对于n位设计，DES的估计错误率较低，为0.9481%，模拟时间较短，模式减少(2^n x 2^n!)-(2^n x 2^n x 2)。同样的技术可以扩展到任何分组密码，包括AES和IDEA-NXT。
{"title":"Static Average Case Power Estimation Technique for Block Ciphers","authors":"Tingcong Ye, D. Vasudevan, Jiaoyan Chen, E. Popovici, M. Schellekens","doi":"10.1109/DSD.2010.105","DOIUrl":"https://doi.org/10.1109/DSD.2010.105","url":null,"abstract":"In this paper a new static average case dynamic power estimation technique is introduced based on the property of randomness preservation for digital circuits. The proposed technique is validated by estimating the average case power for a block cipher, DES with a lower estimation error percentage of 0.9481 % and lesser simulation time with a pattern reduction of (2^n x 2^n!)-(2^n x 2^n x 2) for n bit design. The same technique can be extended to any block cipher, including the AES and IDEA-NXT.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a scalable wormhole switch architecture with a credit based guaranteed service implementation. By means of credits for a service guarantee the architecture is also able to deal with mesochronous GALS systems. We extended a regular wormhole switch architecture with a control unit for service configuration during run-time and modified the arbitration policy. These changes result in a marginal area overhead per switch of approximately 4%. Thus our new architecture provides a simple solution to implement service guarantees without limitation to a fully synchronous system. We synthesized our design with a 65nm technology and achieved a clock frequency of 1GHz. Due to the high clock frequency we are able to get a channel throughput of more than 4GB/sec whereas the total design complexity is 30k gate equivalents.
{"title":"NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems","authors":"T. Kranich, Mladen Berekovic","doi":"10.1109/DSD.2010.30","DOIUrl":"https://doi.org/10.1109/DSD.2010.30","url":null,"abstract":"In this paper we present a scalable wormhole switch architecture with a credit based guaranteed service implementation. By means of credits for a service guarantee the architecture is also able to deal with mesochronous GALS systems. We extended a regular wormhole switch architecture with a control unit for service configuration during run-time and modified the arbitration policy. These changes result in a marginal area overhead per switch of approximately 4%. Thus our new architecture provides a simple solution to implement service guarantees without limitation to a fully synchronous system. We synthesized our design with a 65nm technology and achieved a clock frequency of 1GHz. Due to the high clock frequency we are able to get a channel throughput of more than 4GB/sec whereas the total design complexity is 30k gate equivalents.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122375304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dan Hotoleanu, O. Creţ, A. Suciu, Tamas Györfi, L. Văcariu
This paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.
{"title":"Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration","authors":"Dan Hotoleanu, O. Creţ, A. Suciu, Tamas Györfi, L. Văcariu","doi":"10.1109/DSD.2010.56","DOIUrl":"https://doi.org/10.1109/DSD.2010.56","url":null,"abstract":"This paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using dynamic partial reconfiguration. The design offers a basic framework for easy integration of any additional randomness evaluation tests as well. Due to the integration of both the TRNG and the tests suite in a single FPGA chip, our solution offers new opportunities in the area of random number generation and testing, greatly reducing the time between the generation and the validation of the generated sequences of random bits.","PeriodicalId":356885,"journal":{"name":"2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121289104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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