Pub Date : 2024-01-23DOI: 10.1142/s0129156424400032
Zemiao Dai
Due to the limitations of imaging equipment and image transmission conditions on daily image acquisition, the images acquired are usually low-resolution images, and it will cost a lot of time and economic costs to increase image resolution by upgrading hardware equipment. In this paper, we propose an image super-resolution reconstruction algorithm based on spatio-temporal-dependent residual network MSRN, which fuses multiple features. The algorithm uses the surface feature extraction module to extract the input features of the image, and then uses the deep residual aggregation module to adaptively learn the deep features, and then fuses multiple features and learns the global residual. Finally, the high-resolution image is obtained through the up-sampling module and the reconstruction module. In the model structure, different convolution kernels and jump connections are used to extract more high-frequency information, and spatio-temporal attention mechanism is introduced to focus on more image details. The experimental results show that compared with SRGAN, VDSR and Laplacian Pyramid SRN, the proposed algorithm finally achieves better reconstruction effect, and the image texture details are clearer under different scaling factors. In objective evaluation, the peak signal-to-noise ratio (PSNR) and structure similarity (SSIM) of the proposed algorithm are improved compared with SRGAN.
{"title":"Image Super-Resolution Reconstruction Model Based on Multi-Feature Fusion","authors":"Zemiao Dai","doi":"10.1142/s0129156424400032","DOIUrl":"https://doi.org/10.1142/s0129156424400032","url":null,"abstract":"Due to the limitations of imaging equipment and image transmission conditions on daily image acquisition, the images acquired are usually low-resolution images, and it will cost a lot of time and economic costs to increase image resolution by upgrading hardware equipment. In this paper, we propose an image super-resolution reconstruction algorithm based on spatio-temporal-dependent residual network MSRN, which fuses multiple features. The algorithm uses the surface feature extraction module to extract the input features of the image, and then uses the deep residual aggregation module to adaptively learn the deep features, and then fuses multiple features and learns the global residual. Finally, the high-resolution image is obtained through the up-sampling module and the reconstruction module. In the model structure, different convolution kernels and jump connections are used to extract more high-frequency information, and spatio-temporal attention mechanism is introduced to focus on more image details. The experimental results show that compared with SRGAN, VDSR and Laplacian Pyramid SRN, the proposed algorithm finally achieves better reconstruction effect, and the image texture details are clearer under different scaling factors. In objective evaluation, the peak signal-to-noise ratio (PSNR) and structure similarity (SSIM) of the proposed algorithm are improved compared with SRGAN.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":"68 7","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139604097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-23DOI: 10.1142/s0129156424400044
Ran Li, Juan Dai
The microcontrollers in a camera often capture videos at a low frame rate due to limited processing capability. To satisfy the requirement of high quality of service, low-frame-rate videos are often forged as the high-frame-rate ones by the Frame Rate Up-Conversion (FRUC) operation. Therefore, detecting the existence of FRUC has become a necessary job for secured microcontrollers. In this paper, we propose a data-driven detection to identify whether a video is forged by FRUC. The core of detection is the creation of a large-scale video dataset VifFRUC (Videos forged by FRUC). Various types of forged videos can continue to be added into VifFRUC, making the detection more universal and robust. To match with VifFRUC, we have also designed a neural network, which trains a number of Long Short Term Memory (LSTM) units in parallel to learn the data-driven detection. The parallel LSTM structure of network can continually adapt to the newly added FRUC methods in VifFRUC. Extensive experiments on VifFRUC demonstrate the effectiveness of data-driven detection for FRUC, resulting in the security improvement of microcontrollers.
{"title":"Data-Driven Detection of Video Forgery for Secured Microcontrollers: Dataset and Method","authors":"Ran Li, Juan Dai","doi":"10.1142/s0129156424400044","DOIUrl":"https://doi.org/10.1142/s0129156424400044","url":null,"abstract":"The microcontrollers in a camera often capture videos at a low frame rate due to limited processing capability. To satisfy the requirement of high quality of service, low-frame-rate videos are often forged as the high-frame-rate ones by the Frame Rate Up-Conversion (FRUC) operation. Therefore, detecting the existence of FRUC has become a necessary job for secured microcontrollers. In this paper, we propose a data-driven detection to identify whether a video is forged by FRUC. The core of detection is the creation of a large-scale video dataset VifFRUC (Videos forged by FRUC). Various types of forged videos can continue to be added into VifFRUC, making the detection more universal and robust. To match with VifFRUC, we have also designed a neural network, which trains a number of Long Short Term Memory (LSTM) units in parallel to learn the data-driven detection. The parallel LSTM structure of network can continually adapt to the newly added FRUC methods in VifFRUC. Extensive experiments on VifFRUC demonstrate the effectiveness of data-driven detection for FRUC, resulting in the security improvement of microcontrollers.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":"5 8","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139602985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-23DOI: 10.1142/s0129156424500034
Jitender Kumar, A. N. Mahajan, S. Deswal, Amit Saxena, R. S. Gupta
The gate-all-around (GAA) silicon-on-insulator (SOI) Schottky barrier (SB) nano-wire (NW) MOSFET was recently proposed for low-power and high-frequency analog and radio frequency (RF) circuits. But their use in low-power and high-frequency analog/RF circuits is still under investigation. In this work, basic analog signal processing circuits using gate-all-around SOI-SB-NW MOSFETs are designed for low-power and high-frequency applications. These basic and necessary analog processing circuits are designed for ± 0.3 V and ± 0.25 V power supplies to work on frequencies up to 10 GHz. The analog/RF characteristics of the GAA SOI-SB MOSFET are compared with those of the GAA SB NW MOSFET. The SOI-SB NW MOSFET shows improvements in early voltage, output resistance, and transconductance generation factor. The Silvaco TCAD simulator is used to obtain the results and perform numerical simulations. Simulation results show good analog/RF performance of the analog processing circuits.
{"title":"Design of Low Power Analog/RF Signal Processing Circuits Using 22 nm Silicon-on-Insulator Schottky Barrier Nano-Wire MOSFET","authors":"Jitender Kumar, A. N. Mahajan, S. Deswal, Amit Saxena, R. S. Gupta","doi":"10.1142/s0129156424500034","DOIUrl":"https://doi.org/10.1142/s0129156424500034","url":null,"abstract":"The gate-all-around (GAA) silicon-on-insulator (SOI) Schottky barrier (SB) nano-wire (NW) MOSFET was recently proposed for low-power and high-frequency analog and radio frequency (RF) circuits. But their use in low-power and high-frequency analog/RF circuits is still under investigation. In this work, basic analog signal processing circuits using gate-all-around SOI-SB-NW MOSFETs are designed for low-power and high-frequency applications. These basic and necessary analog processing circuits are designed for ± 0.3 V and ± 0.25 V power supplies to work on frequencies up to 10 GHz. The analog/RF characteristics of the GAA SOI-SB MOSFET are compared with those of the GAA SB NW MOSFET. The SOI-SB NW MOSFET shows improvements in early voltage, output resistance, and transconductance generation factor. The Silvaco TCAD simulator is used to obtain the results and perform numerical simulations. Simulation results show good analog/RF performance of the analog processing circuits.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":"107 12","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139605990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-09DOI: 10.1142/s0129156424500022
Pranjal Jog, R. K. Kumawat
Electric Vehicles (EVs) are powered by a battery mounted in the vehicle, which powers the motor and drives the wheels. Most commercial EVs can be charged by plugging them into a charging station. Such conductive recharging has various drawbacks, including physical plugging of the cable, safety concerns, and charging time. Manually charging EVs might be dangerous due to the chance of an electric spark or disaster. Advances in Wireless Power Transfer (WPT) demonstrate the capacity to transfer significant amounts of electricity over short and medium-range distances. The ultimate purpose of this paper is to improve the efficacy of electric car wireless charging systems. Here, a hybrid optimization-based Artificial Neural Network (ANN) model is applied to improve the efficacy of the WPT model in EVs. To optimize the weights of the ANN classifier, a hybrid approach termed as Grasshopper-Assisted Elephant Herd Optimization (GA-EHO) method is proposed. The GA-EHO is derived through the hybridization of Elephant Herd Optimization (EHO) Algorithm and the Grasshopper Optimization Algorithm (GOA) techniques. Finally, the experimental study reveals that at 70% learning rate, the proposed ANN system achieves a minimal MSE value of 0.0528, which is lower than other current classifiers, such as SVM, LSTM, and CNN.
电动汽车（EV）由安装在车内的电池提供动力，电池为电机提供动力并驱动车轮。大多数商用电动汽车可以通过插入充电站进行充电。这种传导式充电方式有各种缺点，包括电缆的物理插入、安全问题和充电时间。由于可能产生电火花或灾难，手动为电动汽车充电可能很危险。无线电力传输（WPT）技术的进步证明了在中短距离内传输大量电力的能力。本文的最终目的是提高电动汽车无线充电系统的效率。本文采用基于混合优化的人工神经网络（ANN）模型来提高电动汽车 WPT 模型的功效。为了优化 ANN 分类器的权重，本文提出了一种称为 "蚱蜢辅助象群优化（GA-EHO）"的混合方法。GA-EHO 是通过象群优化算法（EHO）和草蜢优化算法（GOA）技术的混合而产生的。最后，实验研究表明，在学习率为 70% 的情况下，所提出的 ANN 系统的最小 MSE 值为 0.0528，低于 SVM、LSTM 和 CNN 等其他现有分类器。
{"title":"A Hybrid Optimization-Based Artificial Neural Network Model for Wireless Power Transfer in Electric Vehicles","authors":"Pranjal Jog, R. K. Kumawat","doi":"10.1142/s0129156424500022","DOIUrl":"https://doi.org/10.1142/s0129156424500022","url":null,"abstract":"Electric Vehicles (EVs) are powered by a battery mounted in the vehicle, which powers the motor and drives the wheels. Most commercial EVs can be charged by plugging them into a charging station. Such conductive recharging has various drawbacks, including physical plugging of the cable, safety concerns, and charging time. Manually charging EVs might be dangerous due to the chance of an electric spark or disaster. Advances in Wireless Power Transfer (WPT) demonstrate the capacity to transfer significant amounts of electricity over short and medium-range distances. The ultimate purpose of this paper is to improve the efficacy of electric car wireless charging systems. Here, a hybrid optimization-based Artificial Neural Network (ANN) model is applied to improve the efficacy of the WPT model in EVs. To optimize the weights of the ANN classifier, a hybrid approach termed as Grasshopper-Assisted Elephant Herd Optimization (GA-EHO) method is proposed. The GA-EHO is derived through the hybridization of Elephant Herd Optimization (EHO) Algorithm and the Grasshopper Optimization Algorithm (GOA) techniques. Finally, the experimental study reveals that at 70% learning rate, the proposed ANN system achieves a minimal MSE value of 0.0528, which is lower than other current classifiers, such as SVM, LSTM, and CNN.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":"450 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138983080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500246
A. F. M. Moshiur Rahman, S. Fan, N. Dutta
A 30-GHz pulse-train is generated using the rational harmonic mode-locking technique, experimentally, using a Mach–Zehnder Lithium Niobate modulator. The width of the pulses is then reduced from 5.8-ps to 1.9-ps by incorporating nonlinear polarization rotation. This phenomenon arises due to the very high nonlinear behavior of the photonic crystal fiber (PCF) added to the ring laser cavity. Numerically solving the Generalized Nonlinear Schrödinger Equation provided insights into the pulse evolution behavior. The relative polarization angle and length of the PCF were varied to study their effects on the pulse-width.
{"title":"Ultra-Short Pulse-Train Generation of 30-GHz Repetition Rate Using Rational Harmonic Mode Locking and Nonlinear Polarization Rotation","authors":"A. F. M. Moshiur Rahman, S. Fan, N. Dutta","doi":"10.1142/s0129156423500246","DOIUrl":"https://doi.org/10.1142/s0129156423500246","url":null,"abstract":"A 30-GHz pulse-train is generated using the rational harmonic mode-locking technique, experimentally, using a Mach–Zehnder Lithium Niobate modulator. The width of the pulses is then reduced from 5.8-ps to 1.9-ps by incorporating nonlinear polarization rotation. This phenomenon arises due to the very high nonlinear behavior of the photonic crystal fiber (PCF) added to the ring laser cavity. Numerically solving the Generalized Nonlinear Schrödinger Equation provided insights into the pulse evolution behavior. The relative polarization angle and length of the PCF were varied to study their effects on the pulse-width.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45120197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500106
A. Rahman, S. Fan, N. Dutta
Optical pulses at high repetition rates are generated using rational harmonic mode locking and saturable absorber made of graphene nanoparticles in a fiber laser. The pulse generation from the fiber laser is modeled by solving the Generalized Nonlinear Schrodinger Equation. The computation involved varying the various saturable absorption parameters, such as linear and nonlinear absorption coefficients. Experimentally stable pulse trains at 20 GHz and 50 GHz are generated with a pulse width of ∼ 2.7 ps. This result agrees with the simulation.
{"title":"Hybrid Mode-Locked Fiber Ring Laser Using Graphene Saturable Absorbers to Generate 20 and 50-GHz Pulse Trains","authors":"A. Rahman, S. Fan, N. Dutta","doi":"10.1142/s0129156423500106","DOIUrl":"https://doi.org/10.1142/s0129156423500106","url":null,"abstract":"Optical pulses at high repetition rates are generated using rational harmonic mode locking and saturable absorber made of graphene nanoparticles in a fiber laser. The pulse generation from the fiber laser is modeled by solving the Generalized Nonlinear Schrodinger Equation. The computation involved varying the various saturable absorption parameters, such as linear and nonlinear absorption coefficients. Experimentally stable pulse trains at 20 GHz and 50 GHz are generated with a pulse width of ∼ 2.7 ps. This result agrees with the simulation.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41430413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500040
R. Raman, J. Grasso, B. Willis
Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.
{"title":"Heating Effects on Nanofabricated Plasmonic Dimers with Interconnects","authors":"R. Raman, J. Grasso, B. Willis","doi":"10.1142/s0129156423500040","DOIUrl":"https://doi.org/10.1142/s0129156423500040","url":null,"abstract":"Plasmonic nanostructures with electrical connections have potential applications as new electro-optic devices due to their strong light–matter interactions. Plasmonic dimers with nanogaps between adjacent nanostructures are especially good at enhancing local electromagnetic (EM) fields at resonance for improved performance. In this study, we use optical extinction measurements and high-resolution electron microscopy imaging to investigate the thermal stability of electrically interconnected plasmonic dimers and their optical and morphological properties. Experimental measurements and finite difference time domain (FDTD) simulations are combined to characterize temperature effects on the plasmonic properties of large arrays of Au nanostructures on glass substrates. Experiments show continuous blue shifts of extinction peaks for heating up to 210°C. Microscopy measurements reveal these peak shifts are due to morphological changes that shrink nanorods and increase nanogap distances. Simulations of the nanostructures before and after heating find good agreement with experiments. Results show that plasmonic properties are maintained after thermal processing, but peak shifts need to be considered for device design.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47904814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500258
W. Alamoudi, B. Saman, R. Gudlavalleti, A. Almalki, J. Chandy, E. Heller, F. Jain
A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.
{"title":"Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters","authors":"W. Alamoudi, B. Saman, R. Gudlavalleti, A. Almalki, J. Chandy, E. Heller, F. Jain","doi":"10.1142/s0129156423500258","DOIUrl":"https://doi.org/10.1142/s0129156423500258","url":null,"abstract":"A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45698744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500192
U. Salahuddin, J. Sun, Chun Jiang Zhu, P. Gao
Microplastics are commonly recognized as environmental and biotic contaminants. The prevalent presence of microplastics in aquatic settings raises concerns about plastic pollution. Therefore, it is critical to develop methods that can eliminate these microplastics with low cost and high effectiveness. This review concisely provides an overview of various methods and technologies for removing microplastics from wastewater and marine environments. Dynamic membranes and membrane bioreactors are effective in removing microplastics from wastewater. Chemical methods such as coagulation and sedimentation, electrocoagulation, and sol-gel reactions can also be used for microplastic removal. Biological methods such as the use of microorganisms and fungi are also effective for microplastic degradation. Advanced filtration technologies like a combination of membrane bioreactor and activated sludge method show high microplastic removal efficiency.
{"title":"Filtration Methods for Microplastic Removal in Wastewater Streams — A Review","authors":"U. Salahuddin, J. Sun, Chun Jiang Zhu, P. Gao","doi":"10.1142/s0129156423500192","DOIUrl":"https://doi.org/10.1142/s0129156423500192","url":null,"abstract":"Microplastics are commonly recognized as environmental and biotic contaminants. The prevalent presence of microplastics in aquatic settings raises concerns about plastic pollution. Therefore, it is critical to develop methods that can eliminate these microplastics with low cost and high effectiveness. This review concisely provides an overview of various methods and technologies for removing microplastics from wastewater and marine environments. Dynamic membranes and membrane bioreactors are effective in removing microplastics from wastewater. Chemical methods such as coagulation and sedimentation, electrocoagulation, and sol-gel reactions can also be used for microplastic removal. Biological methods such as the use of microorganisms and fungi are also effective for microplastic degradation. Advanced filtration technologies like a combination of membrane bioreactor and activated sludge method show high microplastic removal efficiency.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48797649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500234
A. Husawi, R. Gudlavalleti, B. Saman, A. Almalki, J. Chandy, E. Heller, F. Jain
This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.
{"title":"Propagation Delay and Power Dissipation Analysis for a 2-Bit SRAM Using Multi-State SWS Inverter","authors":"A. Husawi, R. Gudlavalleti, B. Saman, A. Almalki, J. Chandy, E. Heller, F. Jain","doi":"10.1142/s0129156423500234","DOIUrl":"https://doi.org/10.1142/s0129156423500234","url":null,"abstract":"This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43830769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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