Pub Date : 2023-07-20DOI: 10.1142/s0129156423500088
Aalvee Asad Kausani, M. Anwar
The fourth fundamental circuit element, the memristor, has become a promising candidate to substantially improve the energy and area efficiencies of circuits as traditional complementary metal-oxide-semiconductor (CMOS) technology is approaching its physical limit. However, a mathematical representation of the experimentally obtained current-voltage characteristic of the memristor is necessary to develop and test memristor-based circuitry in electrical design simulators. Here we have developed a behavioral model for the I-V trace of a Pt/TiO2/Pt memristor that can relate the fitting equations with the physical processes associated with the device in response to applied electrical excitation. Multiple conduction mechanisms are involved in memristor that depend upon its latest state. Therefore, the I-V has distinct segments that altogether form a hysteresis loop pinched at the center. In accordance with the predominant conduction mechanisms at each segment, our model defines the form of the equations. The behavioral model can adequately represent the experimental I-V retrieved from existing work.
{"title":"Behavioral Modeling of the Pinched Hysteresis Loop of a Pt/TiO2/Pt Memristor","authors":"Aalvee Asad Kausani, M. Anwar","doi":"10.1142/s0129156423500088","DOIUrl":"https://doi.org/10.1142/s0129156423500088","url":null,"abstract":"The fourth fundamental circuit element, the memristor, has become a promising candidate to substantially improve the energy and area efficiencies of circuits as traditional complementary metal-oxide-semiconductor (CMOS) technology is approaching its physical limit. However, a mathematical representation of the experimentally obtained current-voltage characteristic of the memristor is necessary to develop and test memristor-based circuitry in electrical design simulators. Here we have developed a behavioral model for the I-V trace of a Pt/TiO2/Pt memristor that can relate the fitting equations with the physical processes associated with the device in response to applied electrical excitation. Multiple conduction mechanisms are involved in memristor that depend upon its latest state. Therefore, the I-V has distinct segments that altogether form a hysteresis loop pinched at the center. In accordance with the predominant conduction mechanisms at each segment, our model defines the form of the equations. The behavioral model can adequately represent the experimental I-V retrieved from existing work.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47815954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500131
Erik Perez, R. Lacomb, F. Jain
This paper presents preliminary results of a high speed 1550 nm indium gallium arsenide (InGaAs)-based mesa-type modified uni-traveling carrier photodiode (M-UTC-PD) structure. Conventional UTC-PD refers to P-I-N type photodiodes which selectively use electrons as active carriers. Photons absorbed in the relatively thin P-type absorber create minority carriers which are field accelerated toward a depleted collector thereby establishing high velocity ballistic transport, making these structures applicable for high speed applications. The M-UTC-PD structure presented uses spatially tailored P-type absorber regions to limit minority carrier generation both in the lateral and axial dimensions. Utilizing an otherwise conventional UTC-PD epitaxial structure where the top P-type layers are undoped, the spatially tailored P-type regions are defined by closed ampoule Zinc diffusion techniques. The M-UTC-PD structure presented utilizes a series of nested p-doped rings within a mesa structure to limit dark current and reduce overall capacitance to improve high speed operation. Two photodiode structures will be investigated for this research project, a conventional UTC-PD structure and a modified structure, utilizing similar device designs, epitaxial designs and fabrication processes. The conventional structure will be utilized for fabrication process development, verification of epi quality and development of rapid prototyping approach toward chip-based testing and subsequent high speed RF testing procedures. Conventional UTC-PD device results will be used as a comparison to quantify the performance of the M-UTC-PD structure utilizing Zn-doped defined p-type absorber regions. Results are given for chip tests of UTC-PD chips verifying epitaxial quality and fabrication process, subsequent testing of packaged devices and RF analysis remains. Process development of the Zn-doped devices is underway, once completed, these devices will be compared to the base design to quantify performance enhancement associated with the modified design.
{"title":"High Speed 1550 nm Indium Gallium Arsenide-Indium Phosphide Photodetector","authors":"Erik Perez, R. Lacomb, F. Jain","doi":"10.1142/s0129156423500131","DOIUrl":"https://doi.org/10.1142/s0129156423500131","url":null,"abstract":"This paper presents preliminary results of a high speed 1550 nm indium gallium arsenide (InGaAs)-based mesa-type modified uni-traveling carrier photodiode (M-UTC-PD) structure. Conventional UTC-PD refers to P-I-N type photodiodes which selectively use electrons as active carriers. Photons absorbed in the relatively thin P-type absorber create minority carriers which are field accelerated toward a depleted collector thereby establishing high velocity ballistic transport, making these structures applicable for high speed applications. The M-UTC-PD structure presented uses spatially tailored P-type absorber regions to limit minority carrier generation both in the lateral and axial dimensions. Utilizing an otherwise conventional UTC-PD epitaxial structure where the top P-type layers are undoped, the spatially tailored P-type regions are defined by closed ampoule Zinc diffusion techniques. The M-UTC-PD structure presented utilizes a series of nested p-doped rings within a mesa structure to limit dark current and reduce overall capacitance to improve high speed operation. Two photodiode structures will be investigated for this research project, a conventional UTC-PD structure and a modified structure, utilizing similar device designs, epitaxial designs and fabrication processes. The conventional structure will be utilized for fabrication process development, verification of epi quality and development of rapid prototyping approach toward chip-based testing and subsequent high speed RF testing procedures. Conventional UTC-PD device results will be used as a comparison to quantify the performance of the M-UTC-PD structure utilizing Zn-doped defined p-type absorber regions. Results are given for chip tests of UTC-PD chips verifying epitaxial quality and fabrication process, subsequent testing of packaged devices and RF analysis remains. Process development of the Zn-doped devices is underway, once completed, these devices will be compared to the base design to quantify performance enhancement associated with the modified design.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48860902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500155
Shuai Chen, Lei Wang
As the crisis of confidence and trust in overseas foundries arises, the industry and academic community are paying increasing attention to Printed Circuit Board (PCB) security. PCB, the backbone of any electronic system hardware, always draws attackers’ attention as it carries system and design information. Numerous ways of PCB tampering (e.g., adding/replacing a component, eavesdropping on a trace and bypassing a connection) can lead to more severe problems, such as Intellectual Property (IP) violation, password leaking, the Internet of Things (IoT) attacks or even more. This paper proposes a technique of active self-defense PCB modules with zero performance overhead. Those protection modules will only be activated when the boards are exposed to the attacks. A set of PCBs with proposed protection modules is fabricated and tested to prove the effectiveness and efficiency of the techniques.
{"title":"PCB Security Modules for Reverse-Engineering Resistant Design","authors":"Shuai Chen, Lei Wang","doi":"10.1142/s0129156423500155","DOIUrl":"https://doi.org/10.1142/s0129156423500155","url":null,"abstract":"As the crisis of confidence and trust in overseas foundries arises, the industry and academic community are paying increasing attention to Printed Circuit Board (PCB) security. PCB, the backbone of any electronic system hardware, always draws attackers’ attention as it carries system and design information. Numerous ways of PCB tampering (e.g., adding/replacing a component, eavesdropping on a trace and bypassing a connection) can lead to more severe problems, such as Intellectual Property (IP) violation, password leaking, the Internet of Things (IoT) attacks or even more. This paper proposes a technique of active self-defense PCB modules with zero performance overhead. Those protection modules will only be activated when the boards are exposed to the attacks. A set of PCBs with proposed protection modules is fabricated and tested to prove the effectiveness and efficiency of the techniques.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46473595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s012915642350026x
F. Jain, R. Gudlavalleti, J. Chandy, E. Heller
This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.
{"title":"Novel Multi-State QDC-QDG FETs and Gate All Around (GAA) FETs for Integrated Logic and QD-NVRAMs","authors":"F. Jain, R. Gudlavalleti, J. Chandy, E. Heller","doi":"10.1142/s012915642350026x","DOIUrl":"https://doi.org/10.1142/s012915642350026x","url":null,"abstract":"This paper presents experimental I-V characteristics of a QDC-QDG FET that exhibited 5-states and has the potential to introduce additional states (e.g. 8) by utilizing Ge QDSL mini-energy sub-bands. Mini-energy bands are formed in an asymmetric Si quantum dot channel (QDC) comprising of two silicon oxide cladded Si quantum dots (QDs), where the upper layer has a smaller core diameter and thicker upper oxide cladding serving as tunnel oxide. Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of Si QD layers in the gate region. This paper also proposes Gate all around (GAA) FETs, when integrated with nonvolatile random access memories (NVRAMs) that have the potential for wafer scale integration, similar to vertical NANDs. Novel Si and Ge Quantum-dot-based device configurations discussed in this paper open the pathway forward to implement hardware platform for emerging applications using low power consumption and smaller footprint.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41646738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500179
R. Gudlavalleti, Jacques Goosen, Tao Liu, Hunter Bradley, Elisa Parent, Abdulmajeed Almalki, Erik Perez, F. Jain
This paper presents fabrication of multi-state inverters incorporating SiOx-cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.
{"title":"Fabrication of Multi-Bit SRAMs Using Quantum Dot Channel (QDC)-Quantum Dot Gate (QDG) FET","authors":"R. Gudlavalleti, Jacques Goosen, Tao Liu, Hunter Bradley, Elisa Parent, Abdulmajeed Almalki, Erik Perez, F. Jain","doi":"10.1142/s0129156423500179","DOIUrl":"https://doi.org/10.1142/s0129156423500179","url":null,"abstract":"This paper presents fabrication of multi-state inverters incorporating SiOx-cladded Si quantum dot in the channel and gate region of driver, load, and access transistors. Experimental characteristics are presented exhibiting 3-state behavior in Quantum-dot Channel (QDC)-Quantum-dot Gate (QDG) FETs having Si quantum dots. It is shown that QDC-QDG-FETs-based enhancement mode inverter configurations are the building blocks of a multi-bit static random access memory (SRAM). QDC-QDG-FETs exhibiting four states can also be used to implement compact 4-state logic and nonvolatile memories or random access nonvolatile memories.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46130052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500143
Md Razuan Hossain, Anur Dhungel, Maisha Sadia, P. Paul, Md. Sakib Hasan
Reservoir Computing (RC) is a type of machine learning inspired by neural processes, which excels at handling complex and time-dependent data while maintaining low training costs. RC systems generate diverse reservoir states by extracting features from raw input and projecting them into a high-dimensional space. One key advantage of RC networks is that only the readout layer needs training, reducing overall training expenses. Memristors have gained popularity due to their similarities to biological synapses and compatibility with hardware implementation using various devices and systems. Chaotic events, which are highly sensitive to initial conditions, undergo drastic changes with minor adjustments. Cascade chaotic maps, in particular, possess greater chaotic properties, making them difficult to predict with memoryless devices. This study aims to predict 1D and 2D cascade chaotic time series using a memristor-based hierarchical RC system.
{"title":"1D and 2D Chaotic Time Series Prediction Using Hierarchical Reservoir Computing System","authors":"Md Razuan Hossain, Anur Dhungel, Maisha Sadia, P. Paul, Md. Sakib Hasan","doi":"10.1142/s0129156423500143","DOIUrl":"https://doi.org/10.1142/s0129156423500143","url":null,"abstract":"Reservoir Computing (RC) is a type of machine learning inspired by neural processes, which excels at handling complex and time-dependent data while maintaining low training costs. RC systems generate diverse reservoir states by extracting features from raw input and projecting them into a high-dimensional space. One key advantage of RC networks is that only the readout layer needs training, reducing overall training expenses. Memristors have gained popularity due to their similarities to biological synapses and compatibility with hardware implementation using various devices and systems. Chaotic events, which are highly sensitive to initial conditions, undergo drastic changes with minor adjustments. Cascade chaotic maps, in particular, possess greater chaotic properties, making them difficult to predict with memoryless devices. This study aims to predict 1D and 2D cascade chaotic time series using a memristor-based hierarchical RC system.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49146541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500052
J. Grasso, Jing Zhao, B. Willis
Volatile organic compounds (VOCs) are ubiquitous in the surroundings, originating from both industrial and natural sources. VOCs directly impact the quality of both indoor and outdoor air and play a significant role in processes such as fruit ripening and the body’s metabolism. VOC monitoring has seen significant growth recently, with an emphasis on developing low-cost, portable sensors capable of both vapor discrimination and concentration measurements. VOC sensing remains challenging, mainly because these compounds are nonreactive, appear in low concentrations and share similar chemical structures that results in poor sensor selectivity. Therefore, individual gas sensors struggle to selectively detect target VOCs in the presence of interferences. Electronic noses overcome these limitations by employing machine learning for pattern recognition from arrays of gas sensors. Here, an electronic nose fabricated with four types of functionalized gold nanoparticles demonstrates rapid detection and quantification of eight types of VOCs at four concentration levels. A robust two-step machine learning pipeline is implemented for classification followed by regression analysis for concentration prediction. Random Forest and support vector machine classifiers show excellent results of 100% accuracy for VOC discrimination, independent of measured concentration levels. Each Random Forest regression analysis exhibits high R2 and low RMSE with an average of 0.999 and 0.002, respectively. These results demonstrate the ability of gold nanoparticle gas sensor arrays for rapid detection and quantification.
{"title":"Utilizing Machine Learning for Rapid Discrimination and Quantification of Volatile Organic Compounds in an Electronic Nose Sensor Array","authors":"J. Grasso, Jing Zhao, B. Willis","doi":"10.1142/s0129156423500052","DOIUrl":"https://doi.org/10.1142/s0129156423500052","url":null,"abstract":"Volatile organic compounds (VOCs) are ubiquitous in the surroundings, originating from both industrial and natural sources. VOCs directly impact the quality of both indoor and outdoor air and play a significant role in processes such as fruit ripening and the body’s metabolism. VOC monitoring has seen significant growth recently, with an emphasis on developing low-cost, portable sensors capable of both vapor discrimination and concentration measurements. VOC sensing remains challenging, mainly because these compounds are nonreactive, appear in low concentrations and share similar chemical structures that results in poor sensor selectivity. Therefore, individual gas sensors struggle to selectively detect target VOCs in the presence of interferences. Electronic noses overcome these limitations by employing machine learning for pattern recognition from arrays of gas sensors. Here, an electronic nose fabricated with four types of functionalized gold nanoparticles demonstrates rapid detection and quantification of eight types of VOCs at four concentration levels. A robust two-step machine learning pipeline is implemented for classification followed by regression analysis for concentration prediction. Random Forest and support vector machine classifiers show excellent results of 100% accuracy for VOC discrimination, independent of measured concentration levels. Each Random Forest regression analysis exhibits high R2 and low RMSE with an average of 0.999 and 0.002, respectively. These results demonstrate the ability of gold nanoparticle gas sensor arrays for rapid detection and quantification.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49537991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500210
A. Mazady, M. Anwar
We report experimental demonstration of Material Implication (IMP) logic using ZnO nanowire-based memristors. The logic is demonstrated with a high-to-low resistance ratio of only five. This imposes much less stringent requirements on memristor performance that can enable IMP logic operation with lower bit error rates. Process independence on memristor and memristor-based IMP logic performance is demonstrated, and a more practical implementation of logic is made by relaxing the restriction imposed on the ranges of the values of on and off state resistances. IMP logic is validated up to a clock frequency of 100 KHz.
{"title":"Memristor-Based Material Implication Logic: Prelude to In-Memory Computing","authors":"A. Mazady, M. Anwar","doi":"10.1142/s0129156423500210","DOIUrl":"https://doi.org/10.1142/s0129156423500210","url":null,"abstract":"We report experimental demonstration of Material Implication (IMP) logic using ZnO nanowire-based memristors. The logic is demonstrated with a high-to-low resistance ratio of only five. This imposes much less stringent requirements on memristor performance that can enable IMP logic operation with lower bit error rates. Process independence on memristor and memristor-based IMP logic performance is demonstrated, and a more practical implementation of logic is made by relaxing the restriction imposed on the ranges of the values of on and off state resistances. IMP logic is validated up to a clock frequency of 100 KHz.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45073963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500180
F. Jain, R. Gudlavalleti, A. Almalki, B. Saman, P-Y. Chan, J. Chandy, F. Papadimitrakopoulos, E. Heller
This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.
{"title":"Enhancing Number of Bits Via Mini-Energy Band Transitions Using Si Quantum Dot Channel (QDC) and Ge Quantum Dot Gate (QDG) FETs and NVRAMs","authors":"F. Jain, R. Gudlavalleti, A. Almalki, B. Saman, P-Y. Chan, J. Chandy, F. Papadimitrakopoulos, E. Heller","doi":"10.1142/s0129156423500180","DOIUrl":"https://doi.org/10.1142/s0129156423500180","url":null,"abstract":"This paper presents multi-state QDC-QDG FET structures that has the potential to introduce additional states (8 or 16) by utilizing additional mini-energy sub-bands. Mini-energy bands are formed in Si quantum dot channel (QDC) comprising two silicon oxide cladded Si quantum dots (QDs). Quantum simulations are presented to show more states when additional two germanium oxide cladded Ge dots are added on top of two Si QD layers in the gate region. With the addition of a control gate oxide layer, we transform the QDC-QDG-FET into a quantum dot (QD) nonvolatile random access memory (NVRAM). Quantum simulations are presented.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43981023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-20DOI: 10.1142/s0129156423500167
Marvin Joshi, Kexin Hu, G. Soto-Valle, Hani Al Jamal, M. Tentzeris
The rapid development and deployment of 5G/mm-Wave technologies for communication, sensing and energy harvesting applications have been on the rise. Consequently, the need for low-cost, scalable, agile and compact RF modules has become more prominent than ever. This paper presents a review of recent efforts in utilizing additive manufacturing techniques such as inkjet printing to sustainably accelerate the massive deployment of 5G/mm-Wave. First, a novel flexible and massively scalable multiple-input, multiple-output (MIMO) tile-based phased array enabled by additively manufactured microstrip-to-microstrip transitions is presented. Next, a novel Rotman-Based harmonic mmID tag for Ultra-Long-Range localization is presented. Finally, low-power, low-cost mm-Wave backscattering modules for localization and orientation sensing are demonstrated.
{"title":"Next Generation RF Modules for 5G, IoT, AR/VR and RFID Applications","authors":"Marvin Joshi, Kexin Hu, G. Soto-Valle, Hani Al Jamal, M. Tentzeris","doi":"10.1142/s0129156423500167","DOIUrl":"https://doi.org/10.1142/s0129156423500167","url":null,"abstract":"The rapid development and deployment of 5G/mm-Wave technologies for communication, sensing and energy harvesting applications have been on the rise. Consequently, the need for low-cost, scalable, agile and compact RF modules has become more prominent than ever. This paper presents a review of recent efforts in utilizing additive manufacturing techniques such as inkjet printing to sustainably accelerate the massive deployment of 5G/mm-Wave. First, a novel flexible and massively scalable multiple-input, multiple-output (MIMO) tile-based phased array enabled by additively manufactured microstrip-to-microstrip transitions is presented. Next, a novel Rotman-Based harmonic mmID tag for Ultra-Long-Range localization is presented. Finally, low-power, low-cost mm-Wave backscattering modules for localization and orientation sensing are demonstrated.","PeriodicalId":35778,"journal":{"name":"International Journal of High Speed Electronics and Systems","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42623841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：