Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00018
Babak Sharifpour, Mohammad Sharifpour, M. Reshadi
Silicon interposer technology or 2.5D stacking is an approach to decrease memory access delay. In the 3D stacking method, the memory stacks are placed on top of the processing chip, and it uses Through Silicon Via vertical links, but in the 2.5D method, the stacked memories are placed on the sides of the processing chip, and data transfer is from the network that lays on the silicon interposer. We examine the interposer network topologies in the 2.5D chip and present Diagonal Mesh with a new routing algorithm for the interposer network. The stacked memories are on two sides of the processing chip, so Diagonal Mesh interconnections can reduce the delay in accessing dynamic memory using diagonal links. Symmetry and short diagonal links are the advantages of the Diagonal Mesh compared to the other topologies. According to the simulation results, the Diagonal Mesh average hop count is lower than Concentrated Mesh and Double Butterfly, and the average packet latency is lower than the compared topologies. Diagonal Mesh improved 19.7 percent in the average hop count and 41.17 percent in the network saturation point compared to Concentrated Mesh.
{"title":"SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC with Introducing a New Routing Algorithm","authors":"Babak Sharifpour, Mohammad Sharifpour, M. Reshadi","doi":"10.1109/SLIP52707.2021.00018","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00018","url":null,"abstract":"Silicon interposer technology or 2.5D stacking is an approach to decrease memory access delay. In the 3D stacking method, the memory stacks are placed on top of the processing chip, and it uses Through Silicon Via vertical links, but in the 2.5D method, the stacked memories are placed on the sides of the processing chip, and data transfer is from the network that lays on the silicon interposer. We examine the interposer network topologies in the 2.5D chip and present Diagonal Mesh with a new routing algorithm for the interposer network. The stacked memories are on two sides of the processing chip, so Diagonal Mesh interconnections can reduce the delay in accessing dynamic memory using diagonal links. Symmetry and short diagonal links are the advantages of the Diagonal Mesh compared to the other topologies. According to the simulation results, the Diagonal Mesh average hop count is lower than Concentrated Mesh and Double Butterfly, and the average packet latency is lower than the compared topologies. Diagonal Mesh improved 19.7 percent in the average hop count and 41.17 percent in the network saturation point compared to Concentrated Mesh.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124021109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00019
Jitesh Choudhary, J. Soumya, Linga Reddy Cenkeramaddi
Application Mapping in Network-on-Chip (NoC) design is considered a vital challenge because of its NP-hard nature. Many efforts are made to address the application mapping problem, but none has satisfied all the requirements. For example, Integer Linear Programming (ILP) has achieved the best possible solution but lacks scalability. Advancements in Machine Learning (ML) have added new dimensions in solving the application mapping problem. This paper proposes RAMAN: Reinforcement Learning (RL) inspired algorithm for mapping applications onto mesh NoC. RAMAN is a modified Q-Learning technique inspired by RL, aiming to achieve the minimum communication cost for the application mapping problem. The results of RAMAN demonstrated that RL has enormous potential to solve application mapping problem without much complexity and computational cost. RAMAN has achieved the communication cost within the 6% of the optimal cost determined by ILP. Considering the computational overheads and complexity, the results of RAMAN are encouraging. Future work will improve RAMAN's performance and provide a new aspect to solve the application mapping problem.
{"title":"RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip","authors":"Jitesh Choudhary, J. Soumya, Linga Reddy Cenkeramaddi","doi":"10.1109/SLIP52707.2021.00019","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00019","url":null,"abstract":"Application Mapping in Network-on-Chip (NoC) design is considered a vital challenge because of its NP-hard nature. Many efforts are made to address the application mapping problem, but none has satisfied all the requirements. For example, Integer Linear Programming (ILP) has achieved the best possible solution but lacks scalability. Advancements in Machine Learning (ML) have added new dimensions in solving the application mapping problem. This paper proposes RAMAN: Reinforcement Learning (RL) inspired algorithm for mapping applications onto mesh NoC. RAMAN is a modified Q-Learning technique inspired by RL, aiming to achieve the minimum communication cost for the application mapping problem. The results of RAMAN demonstrated that RL has enormous potential to solve application mapping problem without much complexity and computational cost. RAMAN has achieved the communication cost within the 6% of the optimal cost determined by ILP. Considering the computational overheads and complexity, the results of RAMAN are encouraging. Future work will improve RAMAN's performance and provide a new aspect to solve the application mapping problem.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129048998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/slip52707.2021.00002
{"title":"2021 ACM/IEEE International Workshop on System-Level Interconnect Pathfinding","authors":"","doi":"10.1109/slip52707.2021.00002","DOIUrl":"https://doi.org/10.1109/slip52707.2021.00002","url":null,"abstract":"","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"1 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134349881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00014
G. Calò, M. Barbiroli, G. Bellanca, D. Bertozzi, F. Fuschini, V. Tralli, G. Serafino, V. Petruzzelli
The realization of on-chip efficient interconnections is one of the most important challenges in developing new computing architectures based on heterogeneous multichip integration. In these architectures, multicore CPUs, GPUs, and memory are densely integrated and need an effective communication layer to exploit their potentialities. In order to overcome the communication bottleneck of these multichip systems, in this work we propose a new approach based on the use of optical wireless switches. These switches can be integrated with an existing Optical Network on Chip as an alternative to ring-based routing matrices with the aim to increase the overall efficiency of the network. In particular, a device allowing on-chip optical wireless interconnections through transmitting and receiving Optical Phased Arrays (OPAs) is presented. In-plane-radiation of simple taper antennas organized as linear antenna arrays is exploited to form $1times N$ and $Ntimes N$ switching matrices. The OPAs design criteria are discussed in details and three-dimensional Finite Difference Time Domain (FDTD) simulation results are used to evaluate the performance in term of transmission loss and crosstalk among the different nodes of a $3 times 3$ wideband switching fabric.
{"title":"Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited)","authors":"G. Calò, M. Barbiroli, G. Bellanca, D. Bertozzi, F. Fuschini, V. Tralli, G. Serafino, V. Petruzzelli","doi":"10.1109/SLIP52707.2021.00014","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00014","url":null,"abstract":"The realization of on-chip efficient interconnections is one of the most important challenges in developing new computing architectures based on heterogeneous multichip integration. In these architectures, multicore CPUs, GPUs, and memory are densely integrated and need an effective communication layer to exploit their potentialities. In order to overcome the communication bottleneck of these multichip systems, in this work we propose a new approach based on the use of optical wireless switches. These switches can be integrated with an existing Optical Network on Chip as an alternative to ring-based routing matrices with the aim to increase the overall efficiency of the network. In particular, a device allowing on-chip optical wireless interconnections through transmitting and receiving Optical Phased Arrays (OPAs) is presented. In-plane-radiation of simple taper antennas organized as linear antenna arrays is exploited to form $1times N$ and $Ntimes N$ switching matrices. The OPAs design criteria are discussed in details and three-dimensional Finite Difference Time Domain (FDTD) simulation results are used to evaluate the performance in term of transmission loss and crosstalk among the different nodes of a $3 times 3$ wideband switching fabric.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115051378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00008
H. Zahedmanesh, I. Ciofi, O. Zografos, M. Badaroglu, K. Croes
Electromigration has been a major reliability concern for nano-interconnects in CMOS applications. With further CMOS miniaturization, the cross-sectional area of nano-interconnects is further scaled resulting in a significant increase of current densities. It has been shown that $j_{max}$ of copper interconnects degrades abruptly at scaled linewidths, predicting increased susceptibility to electromigration. Nevertheless, there is still a dilemma given that the electromigration metrics are typically obtained from electromigration tests on single isolated interconnects and may not be readily translated into metrics for interconnect networks of CMOS designs, which is key for enabling realistic reliability predictions at system-level. In this paper, we demonstrate a physics-based system-level electromigration modelling platform aiming to address the shortcomings of the standard of practice for electromigration compliance checks during the design phase and enhance the accuracy of lifetime predictions from a system viewpoint. The framework is specifically applied to the case of PDN for a 3 nm technology node.
{"title":"A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network","authors":"H. Zahedmanesh, I. Ciofi, O. Zografos, M. Badaroglu, K. Croes","doi":"10.1109/SLIP52707.2021.00008","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00008","url":null,"abstract":"Electromigration has been a major reliability concern for nano-interconnects in CMOS applications. With further CMOS miniaturization, the cross-sectional area of nano-interconnects is further scaled resulting in a significant increase of current densities. It has been shown that $j_{max}$ of copper interconnects degrades abruptly at scaled linewidths, predicting increased susceptibility to electromigration. Nevertheless, there is still a dilemma given that the electromigration metrics are typically obtained from electromigration tests on single isolated interconnects and may not be readily translated into metrics for interconnect networks of CMOS designs, which is key for enabling realistic reliability predictions at system-level. In this paper, we demonstrate a physics-based system-level electromigration modelling platform aiming to address the shortcomings of the standard of practice for electromigration compliance checks during the design phase and enhance the accuracy of lifetime predictions from a system viewpoint. The framework is specifically applied to the case of PDN for a 3 nm technology node.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124403839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00011
G. Sisto, Rongmei Chen, R. Chou, G. V. D. Plas, E. Beyne, Rod Metcalfe, D. Milojevic
In this paper, we describe different design methodologies to bridge the gap between 3D and 2D Integrated Circuits in the Electronic Design Automation framework. An extended version of a Die-by-Die place and route flow for 3D systems is presented, focusing on the power management and timing optimization aspects. The corresponding sign-off methodologies to perform 3D power and timing optimization are developed using commercial tools. For both 3D-aware Multi-Die rail analysis and Static Timing Analysis, sample results on a test design example are included as means to validate the flows.
{"title":"Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)","authors":"G. Sisto, Rongmei Chen, R. Chou, G. V. D. Plas, E. Beyne, Rod Metcalfe, D. Milojevic","doi":"10.1109/SLIP52707.2021.00011","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00011","url":null,"abstract":"In this paper, we describe different design methodologies to bridge the gap between 3D and 2D Integrated Circuits in the Electronic Design Automation framework. An extended version of a Die-by-Die place and route flow for 3D systems is presented, focusing on the power management and timing optimization aspects. The corresponding sign-off methodologies to perform 3D power and timing optimization are developed using commercial tools. For both 3D-aware Multi-Die rail analysis and Static Timing Analysis, sample results on a test design example are included as means to validate the flows.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00009
Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin
As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) are introduced together to continue scaling beyond 5nm using pitch scaling, patterning, and novel 3D cell structures (i.e., Complementary-FET (CFET)). However, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of cost, various standard cell (SDC) heights, SDC architectures, design rules, and back end of line (BEOL) settings. The growing turnaround time (TAT) among standard cell design, design rule optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this work, we propose a DTCO and STCO sensitivity prediction method to improve the performance of DTCO and STCO explorations on block-level area using machine learning techniques. We study and extract the key metrics of block-level designs, SDCs, design rules, and BEOLs. We use a machine learning model to predict the sensitivity of minimum valid block-level area when tuning the design rules and BEOLs with various SDC sets (i.e., different cell heights, Conventional FET, CFET, etc.). We firstly demonstrate that the proposed model achieves 4.05 ×10−3 mean absolute error (MAE) for testing sets to predict block-level area sensitivity of various SDC sets, design rules, and BEOL settings. Then, we show that the proposed model successfully captures the block-level area sensitivity of new SDC sets and new BEOL settings across multiple SDC sets and designs with 3.3 ×10-2and 6 ×10−3MAEs, respectively. Lastly, the proposed modeling approach achieves 5.75 ×10−2MAE on average in the robustness experiment on predicting new designs. The proposed framework provides more than 100× speedups compared to conventional DTCO and STCO exploration flows.
{"title":"Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning","authors":"Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin","doi":"10.1109/SLIP52707.2021.00009","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00009","url":null,"abstract":"As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) are introduced together to continue scaling beyond 5nm using pitch scaling, patterning, and novel 3D cell structures (i.e., Complementary-FET (CFET)). However, numerous DTCO and STCO iterations are needed to continue block-level area scaling with considerations of cost, various standard cell (SDC) heights, SDC architectures, design rules, and back end of line (BEOL) settings. The growing turnaround time (TAT) among standard cell design, design rule optimization, and block-level area evaluation becomes one of the major bottlenecks in DTCO and STCO explorations. In this work, we propose a DTCO and STCO sensitivity prediction method to improve the performance of DTCO and STCO explorations on block-level area using machine learning techniques. We study and extract the key metrics of block-level designs, SDCs, design rules, and BEOLs. We use a machine learning model to predict the sensitivity of minimum valid block-level area when tuning the design rules and BEOLs with various SDC sets (i.e., different cell heights, Conventional FET, CFET, etc.). We firstly demonstrate that the proposed model achieves 4.05 ×10−3 mean absolute error (MAE) for testing sets to predict block-level area sensitivity of various SDC sets, design rules, and BEOL settings. Then, we show that the proposed model successfully captures the block-level area sensitivity of new SDC sets and new BEOL settings across multiple SDC sets and designs with 3.3 ×10-2and 6 ×10−3MAEs, respectively. Lastly, the proposed modeling approach achieves 5.75 ×10−2MAE on average in the robustness experiment on predicting new designs. The proposed framework provides more than 100× speedups compared to conventional DTCO and STCO exploration flows.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125833964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-11-01DOI: 10.1109/SLIP52707.2021.00013
Minmin Jiang, V. Pavlidis
Random Delay Insertion (RDI) has been shown to be an effective countermeasure to side-channel attacks (SCAs) on on-chip power networks. RDI effectively reduces the correlation between the power dissipation and the processed data. However, random delay insertion can degrade circuit performance. Considering the theoretical benefits of delay insertion, this paper proposes a novel methodology that adds delay to interconnect buses to mitigate electromagnetic (EM) SCAs without degrading bus latency. The methodology comprises an efficient delay insertion scheme that hinders electromagnetic attacks, where the delay is inserted into the boundary lines of the bus. As the worst-case bus latency is determined by the lines that drive the maximum cross-coupling capacitance, inserting delay at the boundary lines does not affect the circuit performance as these lines always drive a lower capacitance. The inserted delay improves the security strength of the bus to EM attacks due to the reduction of the correlation between EM emissions and transmitted data, making the methodology effective and directly applicable with negligible overhead. The technique is applied to interposer based off-chip memory buses due to the increasing adoption of 2.5-D integrated systems (although the method is effectively applicable to any interconnect bus). Simulation results show that the technique decreases SNR below 1, which makes EM attacks unsuccessful, and does not increase the (worst-case) bus latency, sustaining the overall circuit performance. Consequently, the proposed method provides a superior EM SCA mitigation method compared to the state-of-the-art. Indeed, theoretical analysis and simulation results demonstrate that the new technique can offer the same level of protection against SCAs with better performance than other hardware RDI countermeasures.
{"title":"Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks","authors":"Minmin Jiang, V. Pavlidis","doi":"10.1109/SLIP52707.2021.00013","DOIUrl":"https://doi.org/10.1109/SLIP52707.2021.00013","url":null,"abstract":"Random Delay Insertion (RDI) has been shown to be an effective countermeasure to side-channel attacks (SCAs) on on-chip power networks. RDI effectively reduces the correlation between the power dissipation and the processed data. However, random delay insertion can degrade circuit performance. Considering the theoretical benefits of delay insertion, this paper proposes a novel methodology that adds delay to interconnect buses to mitigate electromagnetic (EM) SCAs without degrading bus latency. The methodology comprises an efficient delay insertion scheme that hinders electromagnetic attacks, where the delay is inserted into the boundary lines of the bus. As the worst-case bus latency is determined by the lines that drive the maximum cross-coupling capacitance, inserting delay at the boundary lines does not affect the circuit performance as these lines always drive a lower capacitance. The inserted delay improves the security strength of the bus to EM attacks due to the reduction of the correlation between EM emissions and transmitted data, making the methodology effective and directly applicable with negligible overhead. The technique is applied to interposer based off-chip memory buses due to the increasing adoption of 2.5-D integrated systems (although the method is effectively applicable to any interconnect bus). Simulation results show that the technique decreases SNR below 1, which makes EM attacks unsuccessful, and does not increase the (worst-case) bus latency, sustaining the overall circuit performance. Consequently, the proposed method provides a superior EM SCA mitigation method compared to the state-of-the-art. Indeed, theoretical analysis and simulation results demonstrate that the new technique can offer the same level of protection against SCAs with better performance than other hardware RDI countermeasures.","PeriodicalId":358944,"journal":{"name":"2021 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126870751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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