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Conference on Correct Hardware Design and Verification Methods最新文献

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Exact and Efficient Verification of Parameterized Cache Coherence Protocols 参数化缓存一致性协议的精确有效验证
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_22
E. A. Emerson, Vineet Kahlon
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引用次数: 104
Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular 发现规律:描述和分析不太规律的电路
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_4
M. Sheeran
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引用次数: 8
Design and Verification of CoreConnectTM IP Using Esterel 基于Esterel的CoreConnectTM IP设计与验证
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_26
Satnam Singh
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引用次数: 2
On the Correctness of an Intrusion-Tolerant Group Communication Protocol 一种容错组通信协议的正确性
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_21
M. Layouni, J. Hooman, S. Tahar
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引用次数: 8
A Programming Language Based Analysis of Operand Forwarding 基于编程语言的操作数转发分析
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_24
Lennart Beringer
{"title":"A Programming Language Based Analysis of Operand Forwarding","authors":"Lennart Beringer","doi":"10.1007/978-3-540-39724-3_24","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_24","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116213717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Convergence Testing in Term-Level Bounded Model Checking 项级有界模型检验的收敛性检验
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_31
R. Bryant, Shuvendu K. Lahiri, S. Seshia
{"title":"Convergence Testing in Term-Level Bounded Model Checking","authors":"R. Bryant, Shuvendu K. Lahiri, S. Seshia","doi":"10.1007/978-3-540-39724-3_31","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_31","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123325278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
The Charme of Abstract Entities 抽象实体的魅力
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_2
F. Somenzi
{"title":"The Charme of Abstract Entities","authors":"F. Somenzi","doi":"10.1007/978-3-540-39724-3_2","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_2","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Hazards-Based Correctness Statement for Pipelined Circuits 基于危险的流水线电路正确性声明
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_8
M. Aagaard
{"title":"A Hazards-Based Correctness Statement for Pipelined Circuits","authors":"M. Aagaard","doi":"10.1007/978-3-540-39724-3_8","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_8","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127742840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
CTL May Be Ambiguous When Model Checking Moore Machines 模型检查摩尔机时CTL可能有歧义
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_16
Cédric Roux, Emmanuelle Encrenaz-Tiphène
{"title":"CTL May Be Ambiguous When Model Checking Moore Machines","authors":"Cédric Roux, Emmanuelle Encrenaz-Tiphène","doi":"10.1007/978-3-540-39724-3_16","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_16","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122133544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking 结合对称约简和符号表示进行高效模型检验
Conference on Correct Hardware Design and Verification Methods
Pub Date : 2003-10-21 DOI: 10.1007/978-3-540-39724-3_20
E. Allen Emerson, T. Wahl
{"title":"On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking","authors":"E. Allen Emerson, T. Wahl","doi":"10.1007/978-3-540-39724-3_20","DOIUrl":"https://doi.org/10.1007/978-3-540-39724-3_20","url":null,"abstract":"","PeriodicalId":363695,"journal":{"name":"Conference on Correct Hardware Design and Verification Methods","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124628804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
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