Pub Date : 2017-09-18DOI: 10.1109/FDL.2017.8303894
Guillaume Baudart, T. Bourke, Marc Pouzet
The synchronous language Lustre and its descendants have long been used to program and model discrete con-trollers. Recent work shows how to mix discrete and continuous elements in a Lustre-like language called Zélus. The resulting hybrid programs are deterministic and can be simulated with a numerical solver. In this article, we focus on a subset of hybrid programs where continuous behaviors are expressed using timers, nondeterministic guards, and invariants, as in Timed Safety Automata. We propose a source-to-source compilation pass to generate discrete code that, coupled with standard operations on Difference-Bound Matrices, produces symbolic traces that each represent a set of concrete traces.
{"title":"Symbolic simulation of dataflow synchronous programs with timers","authors":"Guillaume Baudart, T. Bourke, Marc Pouzet","doi":"10.1109/FDL.2017.8303894","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303894","url":null,"abstract":"The synchronous language Lustre and its descendants have long been used to program and model discrete con-trollers. Recent work shows how to mix discrete and continuous elements in a Lustre-like language called Zélus. The resulting hybrid programs are deterministic and can be simulated with a numerical solver. In this article, we focus on a subset of hybrid programs where continuous behaviors are expressed using timers, nondeterministic guards, and invariants, as in Timed Safety Automata. We propose a source-to-source compilation pass to generate discrete code that, coupled with standard operations on Difference-Bound Matrices, produces symbolic traces that each represent a set of concrete traces.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128780496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-18DOI: 10.1109/FDL.2017.8303897
Arthur Kalsing, L. Fesquet, C. Aktouf
Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and manipulation with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Language (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a completely automated tool which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.
满足低功耗设计的要求是半导体行业面临的真正挑战。在过去的几年里，许多新的方法被引入来帮助工程师处理日益复杂的芯片设计。其中一种方法是基于统一功率格式(Unified Power Format, UPF)的功率意图描述，它首次定义了一种结构化的标准语言，用于在设计中注释功率意图。这项工作旨在进一步改善UPF标准在行业中的部署，提出一种方法，可以通过自动检测功率意图不一致来实现设计编辑和操作。这项工作演示了如何高度关联UPF和硬件描述语言(HDL)，以便跟踪由于任何一种描述的修改而导致的功率意图不一致。从长远来看，最终的目标是提供一个完全自动化的工具，它可以捕获HDL代码中的变化并相应地修改UPF(反之亦然)。给出了一个测试用例来说明所开发的设计方法的能力。
{"title":"Towards consistency checking between HDL and UPF descriptions","authors":"Arthur Kalsing, L. Fesquet, C. Aktouf","doi":"10.1109/FDL.2017.8303897","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303897","url":null,"abstract":"Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and manipulation with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Language (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a completely automated tool which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133227508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-18DOI: 10.1109/FDL.2017.8303893
R. V. Hanxleden, T. Bourke, A. Girault
We address the problem of synchronous programs that cannot be easily executed in a classical time-triggered or event-triggered execution loop. We propose a novel approach, referred to as dynamic ticks, that reconciles the semantic timing abstraction of the synchronous approach with the desire to give the application fine-grained control over its real-time behavior. The main idea is to allow the application to dynamically specify its own wake-up times rather than ceding their control to the environment. As we illustrate in this paper, synchronous languages such as Esterel are already well equipped for this; no language extensions are needed. All that is required is a rather minor adjustment of the way the tick function is called.
{"title":"Real-time ticks for synchronous programming","authors":"R. V. Hanxleden, T. Bourke, A. Girault","doi":"10.1109/FDL.2017.8303893","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303893","url":null,"abstract":"We address the problem of synchronous programs that cannot be easily executed in a classical time-triggered or event-triggered execution loop. We propose a novel approach, referred to as dynamic ticks, that reconciles the semantic timing abstraction of the synchronous approach with the desire to give the application fine-grained control over its real-time behavior. The main idea is to allow the application to dynamically specify its own wake-up times rather than ceding their control to the environment. As we illustrate in this paper, synchronous languages such as Esterel are already well equipped for this; no language extensions are needed. All that is required is a rather minor adjustment of the way the tick function is called.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134409638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303902
M. Safar
The ISO 26262 defines discrete Automotive Safety Integrity Levels (ASILs) to enforce functional safety. Each component in the automotive system under development must have an associated ASIL. Higher ASIL implies more development cost and effort. ASIL decomposition allows reducing ASIL allocated to components whose joint failure is the only cause for the violation of a safety goal. Fault trees are widely used in the safety analysis process and hence in the ASIL allocation. In this paper, we present a new approach for solving the ASIL decomposition problem using Satisfiability Modulo Theories (SMT). The fault tree structure is fully represented in SMT. Compared to other approaches for ASIL decomposition; our approach eliminates the need of finding the Minimal Cut Set (MCS) of the fault tree. Moreover, it does not require assigning a numerical cost value for each ASIL. Recent emerging trend in powerful SMT solvers for solving objective functions is utilized to find the optimal ASIL decomposition.
ISO 26262定义了离散的汽车安全完整性等级(asil)来加强功能安全。正在开发的汽车系统中的每个组件都必须具有相关的ASIL。更高的ASIL意味着更多的开发成本和努力。ASIL分解允许减少分配给那些联合故障是违反安全目标的唯一原因的组件的ASIL。故障树在安全分析过程中得到了广泛的应用，因此也被广泛应用于ASIL的分配中。本文提出了一种利用可满足模理论(SMT)求解ASIL分解问题的新方法。故障树结构在SMT中得到了完整的表示。与其它ASIL分解方法相比;该方法消除了寻找故障树最小割集(MCS)的需要。此外，它不需要为每个ASIL分配一个数值成本值。利用最近出现的用于求解目标函数的强大SMT求解器的趋势来寻找最优的ASIL分解。
{"title":"Asil decomposition using SMT","authors":"M. Safar","doi":"10.1109/FDL.2017.8303902","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303902","url":null,"abstract":"The ISO 26262 defines discrete Automotive Safety Integrity Levels (ASILs) to enforce functional safety. Each component in the automotive system under development must have an associated ASIL. Higher ASIL implies more development cost and effort. ASIL decomposition allows reducing ASIL allocated to components whose joint failure is the only cause for the violation of a safety goal. Fault trees are widely used in the safety analysis process and hence in the ASIL allocation. In this paper, we present a new approach for solving the ASIL decomposition problem using Satisfiability Modulo Theories (SMT). The fault tree structure is fully represented in SMT. Compared to other approaches for ASIL decomposition; our approach eliminates the need of finding the Minimal Cut Set (MCS) of the fault tree. Moreover, it does not require assigning a numerical cost value for each ASIL. Recent emerging trend in powerful SMT solvers for solving objective functions is utilized to find the optimal ASIL decomposition.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115244366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303891
Essayas Gebrewahid, Z. Ul-Abdin
Manycore architectures are dominating the development of advanced embedded computing due to the computational and power demand of high performance applications. This has introduced an additional complexity with regard to the efficient exploitation of the underlying hardware and the development of efficient parallel implementations. To tackle this we model applications using a dataflow programming language, perform high-level transformations of dataflow actors, and generate native code by using our compilation framework. This paper presents the actor fission transformations of our Cal2Many compilation framework. The transformations have facilitated the mapping of big dataflow actors on memory restricted embedded manycores, increased the utilization of the hardware, and enabled support for task and data-level parallelism. We have applied the actor transformations to two blocks of MPEG-4 decoder and executed it on the Epiphany manycore architecture. The result shows the practicality and feasibility of our approach.
{"title":"Actor fission transformations for executing dataflow programs on manycores","authors":"Essayas Gebrewahid, Z. Ul-Abdin","doi":"10.1109/FDL.2017.8303891","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303891","url":null,"abstract":"Manycore architectures are dominating the development of advanced embedded computing due to the computational and power demand of high performance applications. This has introduced an additional complexity with regard to the efficient exploitation of the underlying hardware and the development of efficient parallel implementations. To tackle this we model applications using a dataflow programming language, perform high-level transformations of dataflow actors, and generate native code by using our compilation framework. This paper presents the actor fission transformations of our Cal2Many compilation framework. The transformations have facilitated the mapping of big dataflow actors on memory restricted embedded manycores, increased the utilization of the hardware, and enabled support for task and data-level parallelism. We have applied the actor transformations to two blocks of MPEG-4 decoder and executed it on the Epiphany manycore architecture. The result shows the practicality and feasibility of our approach.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303899
A. Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, J. Wray, G. Lukyanov, S. Mileiko, Joe Scott, A. Yakovlev, Andrew D. Brown
Graphs are important in many applications however their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analysed up to 1000× faster than on a conventional computer.
{"title":"Language and hardware acceleration backend for graph processing","authors":"A. Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, J. Wray, G. Lukyanov, S. Mileiko, Joe Scott, A. Yakovlev, Andrew D. Brown","doi":"10.1109/FDL.2017.8303899","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303899","url":null,"abstract":"Graphs are important in many applications however their analysis on conventional computer architectures is generally inefficient because it involves highly irregular access to memory when traversing vertices and edges. As an example, when finding a path from a source vertex to a target one the performance is typically limited by the memory bottleneck whereas the actual computation is trivial. This paper presents a methodology for embedding graphs into silicon, where graph vertices become finite state machines communicating via the graph edges. With this approach many common graph analysis tasks can be performed by propagating signals through the physical graph and measuring signal propagation time using the on-chip clock distribution network. This eliminates the memory bottleneck and allows thousands of vertices to be processed in parallel. We present a domain-specific language for graph description and transformation, and demonstrate how it can be used to translate application graphs into an FPGA board, where they can be analysed up to 1000× faster than on a conventional computer.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129093168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303896
Stefano Centomo, M. Lora, A. Portaluri, F. Stefanni, F. Fummi
Simulation of accurate HW models is usually required to verify Embedded SW. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. This paper proposes the automatic generation of cycle-accurate Simulink blocks from the two most popular HW description languages: VHDL and Verilog. The methodology starts from an IP modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction procedure to produce a functionally equivalent cycle-accurate model of the IP. Then, it proposes two alternative mapping and code-generation techniques. The first one relies on the portable FMI standard, while the other one exploits Mathworks' proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex and computationally demanding co-simulation frameworks: a valuable feature when developing complex heterogeneous systems. A set of RTL IPs are used to compare the proposed approach to state-of-the-art co-simulation techniques. Furthermore, the experiments presented in this paper compares the two proposed alternatives to highlight their advantages and drawbacks.
{"title":"Automatic generation of cycle-accurate Simulink blocks from hdl ips","authors":"Stefano Centomo, M. Lora, A. Portaluri, F. Stefanni, F. Fummi","doi":"10.1109/FDL.2017.8303896","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303896","url":null,"abstract":"Simulation of accurate HW models is usually required to verify Embedded SW. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. This paper proposes the automatic generation of cycle-accurate Simulink blocks from the two most popular HW description languages: VHDL and Verilog. The methodology starts from an IP modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction procedure to produce a functionally equivalent cycle-accurate model of the IP. Then, it proposes two alternative mapping and code-generation techniques. The first one relies on the portable FMI standard, while the other one exploits Mathworks' proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex and computationally demanding co-simulation frameworks: a valuable feature when developing complex heterogeneous systems. A set of RTL IPs are used to compare the proposed approach to state-of-the-art co-simulation techniques. Furthermore, the experiments presented in this paper compares the two proposed alternatives to highlight their advantages and drawbacks.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126490360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303890
Enrico Fraccaroli, F. Stefanni, F. Fummi, Mark Zwolinski
Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.
{"title":"Fault analysis in analog circuits through language manipulation and abstraction","authors":"Enrico Fraccaroli, F. Stefanni, F. Fummi, Mark Zwolinski","doi":"10.1109/FDL.2017.8303890","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303890","url":null,"abstract":"Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132849173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303892
Sarah Chabane, R. Ameur-Boulifa, M. Mezghiche
The necessity of handling the increasing complexity of embedded systems has led to the growth of reuse-based design. At the same time, the systems must still satisfy strict requirements on reliability and correctness. This paper proposes a formal analysis of parallel composition of I/O automata. This analysis leads to identification of novel composition rules guaranteeing the correctness-by-construction, and will provide a basis for a sound compositional development of components (Intellectual Property blocks).
{"title":"Rethinking of I/O-automata composition","authors":"Sarah Chabane, R. Ameur-Boulifa, M. Mezghiche","doi":"10.1109/FDL.2017.8303892","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303892","url":null,"abstract":"The necessity of handling the increasing complexity of embedded systems has led to the growth of reuse-based design. At the same time, the systems must still satisfy strict requirements on reliability and correctness. This paper proposes a formal analysis of parallel composition of I/O automata. This analysis leads to identification of novel composition rules guaranteeing the correctness-by-construction, and will provide a basis for a sound compositional development of components (Intellectual Property blocks).","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116634565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303895
J. Aguado, Michael Mendler, J. Wang, Bruno Bodin, P. Roop
In this paper we propose a WCRT analysis technique for synchronous programs, executed as sequential or multi-threaded code, based on formal power series in min-max-plus algebra. The algebraic model constitutes the first fully declarative timing-aware semantics of synchronous programs with arbitrary hierarchical control-flow structure. Under signal abstraction this model permits efficient compositional WCRT analyses based on structural boxes as the unit of composition. The algebraic model leads to a sound methodology to deal with the state space explosion arising from tick alignment of parallel composition by reduction to the maximum weighted clique problem.
{"title":"Compositional timing-aware semantics for synchronous programming","authors":"J. Aguado, Michael Mendler, J. Wang, Bruno Bodin, P. Roop","doi":"10.1109/FDL.2017.8303895","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303895","url":null,"abstract":"In this paper we propose a WCRT analysis technique for synchronous programs, executed as sequential or multi-threaded code, based on formal power series in min-max-plus algebra. The algebraic model constitutes the first fully declarative timing-aware semantics of synchronous programs with arbitrary hierarchical control-flow structure. Under signal abstraction this model permits efficient compositional WCRT analyses based on structural boxes as the unit of composition. The algebraic model leads to a sound methodology to deal with the state space explosion arising from tick alignment of parallel composition by reduction to the maximum weighted clique problem.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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