Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303901
J. Bastos, Bram van der Sanden, O. Donk, J. Voeten, S. Stuijk, R. Schiffelers, H. Corporaal
System design is a difficult process with many design-choices for which the impact may be difficult to foresee. Manufacturing system design is no exception to this. Increased use of flexible manufacturing systems which are able to perform different operations/use-cases further raises the design complexity. One important criterion to consider is the overall makespan and associated critical path for the different use-cases of the system. Stochastic critical path analysis plays a fundamental role in providing useful feedback for system designers to evaluate alternative specifications, which traditional fixed-time analysis cannot. In this paper, we extend our formal model-based framework, for the specification and design of manufacturing systems, with stochastic analysis abilities by associating a criticality index to each action performed by the system. This index can then be visualized and used within the framework such that a system designer can make better informed decisions. We propose a Monte-Carlo method as an estimation algorithm and we explicitly define and use confidence intervals to achieve an acceptable estimation error. We further demonstrate the use of the extended framework and stochastic analysis with an example manufacturing system.
{"title":"Identifying bottlenecks in manufacturing systems using stochastic criticality analysis","authors":"J. Bastos, Bram van der Sanden, O. Donk, J. Voeten, S. Stuijk, R. Schiffelers, H. Corporaal","doi":"10.1109/FDL.2017.8303901","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303901","url":null,"abstract":"System design is a difficult process with many design-choices for which the impact may be difficult to foresee. Manufacturing system design is no exception to this. Increased use of flexible manufacturing systems which are able to perform different operations/use-cases further raises the design complexity. One important criterion to consider is the overall makespan and associated critical path for the different use-cases of the system. Stochastic critical path analysis plays a fundamental role in providing useful feedback for system designers to evaluate alternative specifications, which traditional fixed-time analysis cannot. In this paper, we extend our formal model-based framework, for the specification and design of manufacturing systems, with stochastic analysis abilities by associating a criticality index to each action performed by the system. This index can then be visualized and used within the framework such that a system designer can make better informed decisions. We propose a Monte-Carlo method as an estimation algorithm and we explicitly define and use confidence intervals to achieve an acceptable estimation error. We further demonstrate the use of the extended framework and stochastic analysis with an example manufacturing system.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125961742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303898
V. Herdt, H. M. Le, Daniel Große, R. Drechsler
Efficient power management is very important for modern System-on-Chip to satisfy the conflicting demands on high performance and low power consumption. Nowadays, global power management is mostly implemented in firmware (FW) due to the relative ease of development and its flexibility. Recent advances in system-level power modeling and estimation open up opportunities for early validation of these FW-based power management strategies. In this paper, we propose a novel approach for this purpose using SystemC-based Virtual Prototypes (VPs) and constrained random (CR) techniques. The CR-generated representative system workloads are executed in a power-aware FW/VP co-simulation to validate that available performance and power budgets are satisfied. As a proof-of-concept, we demonstrate our power validation approach on the LEON3-based SoCRocket VP.
{"title":"Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach","authors":"V. Herdt, H. M. Le, Daniel Große, R. Drechsler","doi":"10.1109/FDL.2017.8303898","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303898","url":null,"abstract":"Efficient power management is very important for modern System-on-Chip to satisfy the conflicting demands on high performance and low power consumption. Nowadays, global power management is mostly implemented in firmware (FW) due to the relative ease of development and its flexibility. Recent advances in system-level power modeling and estimation open up opportunities for early validation of these FW-based power management strategies. In this paper, we propose a novel approach for this purpose using SystemC-based Virtual Prototypes (VPs) and constrained random (CR) techniques. The CR-generated representative system workloads are executed in a power-aware FW/VP co-simulation to validate that available performance and power budgets are satisfied. As a proof-of-concept, we demonstrate our power validation approach on the LEON3-based SoCRocket VP.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123295962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.1109/FDL.2017.8303900
Liang Wang, Xiaohang Wang, Ho-fung Leung, T. Mak
Due to technology scaling, lifetime reliability is becoming one of major design constraints in the design of future many-core systems. In this paper, we propose a novel runtime mapping scheme which can dynamically map the applications given a lifetime reliability constraint. A borrowing strategy is adopted to manage the lifetime in a long-term scale, and the lifetime constraint can be relaxed in short-term scale when the communication performance requirement is high. The through-put can be improved because the communication performance of communication intensive applications is optimized, and mean-while the waiting time of computation intensive application is reduced. An improved neighborhood allocation method is proposed for the runtime mapping scheme. Moreover, we propose a method to effectively classify communication intensive applications and computation intensive applications. The experimental results show that compared to the state-of-the-art lifetime-constrained mapping, the proposed scheme has more than 20% throughput improvement in average.
{"title":"Runtime task mapping for lifetime budgeting in many-core systems","authors":"Liang Wang, Xiaohang Wang, Ho-fung Leung, T. Mak","doi":"10.1109/FDL.2017.8303900","DOIUrl":"https://doi.org/10.1109/FDL.2017.8303900","url":null,"abstract":"Due to technology scaling, lifetime reliability is becoming one of major design constraints in the design of future many-core systems. In this paper, we propose a novel runtime mapping scheme which can dynamically map the applications given a lifetime reliability constraint. A borrowing strategy is adopted to manage the lifetime in a long-term scale, and the lifetime constraint can be relaxed in short-term scale when the communication performance requirement is high. The through-put can be improved because the communication performance of communication intensive applications is optimized, and mean-while the waiting time of computation intensive application is reduced. An improved neighborhood allocation method is proposed for the runtime mapping scheme. Moreover, we propose a method to effectively classify communication intensive applications and computation intensive applications. The experimental results show that compared to the state-of-the-art lifetime-constrained mapping, the proposed scheme has more than 20% throughput improvement in average.","PeriodicalId":370459,"journal":{"name":"2017 Forum on Specification and Design Languages (FDL)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133699652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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