Pub Date : 2015-10-01DOI: 10.1109/RTEST.2015.7369843
Javad Ebrahimian Amiri, M. Kargahi
Real-time operating systems play important roles in developing many of today's embedded systems. Majority of these embedded systems have intense interactions with the environment through I/O devices, namely sensors and actuators. Interrupts are often used by the operating systems to handle these interactions through executing the corresponding interrupt service routines (ISRs). ISRs are usually executed non-preemptively at some priorities higher than system tasks. Depending on the interrupt frequency, this prioritization can result in problems like unresponsiveness and unpredictability in the system, even for the high priority tasks. This incurs a type of priority inversion which we call it ISR-task priority inversion (ITPI). This paper uses threaded interrupts and employs the priority inheritance protocol (PIP) to enforce each interrupt service thread (IST) to be executed at its owner's priority, causing less interference with higher priority tasks. Two PIP-based approaches are proposed and implemented: 1) Static priority linked list, which uses PIP only when a task starts; experimental results show that this approach can tolerate some simple forms of ITPI, and 2) Dynamic priority bitmap, which employs PIP whenever a task needs an IST; experiments show that more complex forms of ITPI can be tolerated with this approach. The almost extensive experimental results show that using the dynamic priority approach enhances the real-time system predictability compared to the common approaches.
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Pub Date : 2015-10-01DOI: 10.1109/RTEST.2015.7369849
Roghayeh Mojarad, H. Zarandi
In this paper, two anomaly correction methods are proposed which are based on Markov and Stide detection methods. Both methods consist of three steps: 1) Training, 2) Anomaly detection and 3) Anomaly Correction. In training step, the Morkov-based method constructs a transition matrix; Stidebased method makes a database by events with their frequency. In detection step, when the probability of transition from previous event to current event does not reach a predefined threshold, the morkov-based method detects an anomaly. While, if frequency of unmatched events exceeds from the threshold value, Stide-based method determined an anomaly. In the correction step, the methods check the defined constraints for each anomalous event to find source of anomaly and a suitable way to correct the anomalous event. Evaluation of the proposed methods are done using a total of 7000 data sets. The window size of corrector and the number of injected anomalies varied between 3 and 5, 1 and 7, respectively. The experiments have been done to measure the correction coverage rate for Markov-based and Stide-based methods which are on average 77.66% and 60.9%, respectively. Area consumptions in Makov-based and Stide-based methods are on average 415.48μm2 and 239.61μm2, respectively.
{"title":"Two effective anomaly correction methods in embedded systems","authors":"Roghayeh Mojarad, H. Zarandi","doi":"10.1109/RTEST.2015.7369849","DOIUrl":"https://doi.org/10.1109/RTEST.2015.7369849","url":null,"abstract":"In this paper, two anomaly correction methods are proposed which are based on Markov and Stide detection methods. Both methods consist of three steps: 1) Training, 2) Anomaly detection and 3) Anomaly Correction. In training step, the Morkov-based method constructs a transition matrix; Stidebased method makes a database by events with their frequency. In detection step, when the probability of transition from previous event to current event does not reach a predefined threshold, the morkov-based method detects an anomaly. While, if frequency of unmatched events exceeds from the threshold value, Stide-based method determined an anomaly. In the correction step, the methods check the defined constraints for each anomalous event to find source of anomaly and a suitable way to correct the anomalous event. Evaluation of the proposed methods are done using a total of 7000 data sets. The window size of corrector and the number of injected anomalies varied between 3 and 5, 1 and 7, respectively. The experiments have been done to measure the correction coverage rate for Markov-based and Stide-based methods which are on average 77.66% and 60.9%, respectively. Area consumptions in Makov-based and Stide-based methods are on average 415.48μm2 and 239.61μm2, respectively.","PeriodicalId":376270,"journal":{"name":"2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123020970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-10-01DOI: 10.1109/RTEST.2015.7369845
R. Nazari, Nezam Rohbani, Hamed Farbeh, Z. Shirmohammadi, S. Miremadi
Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible.
{"title":"A2CM2: aging-aware cache memory management technique","authors":"R. Nazari, Nezam Rohbani, Hamed Farbeh, Z. Shirmohammadi, S. Miremadi","doi":"10.1109/RTEST.2015.7369845","DOIUrl":"https://doi.org/10.1109/RTEST.2015.7369845","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes uniformly stress condition for each line. The simulation results show that the proposed technique reduces the NBTI effect in I-cache significantly as compared to normal operation. Moreover, the energy consumption and the performance overheads of the proposed technique are negligible.","PeriodicalId":376270,"journal":{"name":"2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123732427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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