Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274029
V. Mikos, T. Nakura, K. Asada
Stochastic TDCs excel in high resolution at narrow dynamic ranges by employing comparators which have their decision influenced by PVT variations. As the functionality relies on these variations, a transfer function akin to the Gaussian distribution ensues, which is non-linear. We propose a theoretical derivation of the non-linearity analysis and use it to find the stochastic TDC's effective resolution and optimal dynamic range. Software and circuit Monte Carlo simulations are conducted in support of the theoretical findings, where the circuit employs comparators implemented in 180nm CMOS technology.
{"title":"Non-linearity analysis of stochastic time-to-digital converter","authors":"V. Mikos, T. Nakura, K. Asada","doi":"10.1109/ACQED.2015.7274029","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274029","url":null,"abstract":"Stochastic TDCs excel in high resolution at narrow dynamic ranges by employing comparators which have their decision influenced by PVT variations. As the functionality relies on these variations, a transfer function akin to the Gaussian distribution ensues, which is non-linear. We propose a theoretical derivation of the non-linearity analysis and use it to find the stochastic TDC's effective resolution and optimal dynamic range. Software and circuit Monte Carlo simulations are conducted in support of the theoretical findings, where the circuit employs comparators implemented in 180nm CMOS technology.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274033
Masahiro Kano, T. Nakura, K. Asada
This paper proposes an active resonant power supply noise cancelling with fast voltage drop sensor using the combination of delay-locked loop (DLL) and vernier time-to-digital converter (TDC). Also, we propose the capacitor selector circuit realizing the active insertion of capacitors in less silicon area. These components enable one clock noise detection with fine resolution. Simulation results show that our noise sensor detects 54 mV voltage drop in one clock cycle and cancels 28% of the supply noise by the active charge injection. The proposed circuits use the silicon area about 27 times more effectively than conventional passive decaps.
{"title":"Resonant power supply noise cancelling with noise detector based in DLL and vernier TDC","authors":"Masahiro Kano, T. Nakura, K. Asada","doi":"10.1109/ACQED.2015.7274033","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274033","url":null,"abstract":"This paper proposes an active resonant power supply noise cancelling with fast voltage drop sensor using the combination of delay-locked loop (DLL) and vernier time-to-digital converter (TDC). Also, we propose the capacitor selector circuit realizing the active insertion of capacitors in less silicon area. These components enable one clock noise detection with fine resolution. Simulation results show that our noise sensor detects 54 mV voltage drop in one clock cycle and cancels 28% of the supply noise by the active charge injection. The proposed circuits use the silicon area about 27 times more effectively than conventional passive decaps.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274024
J. J. Tay, M. Wong, M. Wong, C. Zhang, I. Hijazin
Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.
{"title":"Compact FPGA implementation of PRESENT with Boolean S-Box","authors":"J. J. Tay, M. Wong, M. Wong, C. Zhang, I. Hijazin","doi":"10.1109/ACQED.2015.7274024","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274024","url":null,"abstract":"Ever since the conception of the ideology known as the Internet of Things (IoT), our world is slowly approaching the brink of mankind's next technological revolution. The realization of IoT requires an enormous amount of sensor nodes to acquire inputs from the connected objects. Due to the lightweight nature of these sensors, constraints emerge in the form of limited power supply and area for the implementation of information security mechanism. To ensure security in the data transmitted by these sensors, lightweight cryptographic solutions are required. In this work, our goal is to implement a compact PRESENT cipher onto a Field Programmable Gate Array (FPGA) platform. Our proposed design uses an 8-bit datapath to reduce hardware size. Instead of a traditional look-up table (LUT) based S-Box, we have implemented a Boolean S-Box through Karnaugh mapping. Further factorization is also done to reduce the size of the Boolean S-Box. As a result, we have achieved the smallest FPGA implementation of the PRESENT cipher to date, requiring only 62 slices on the Virtex-5 XC5VLX50 platform. Our design also features a respectable throughput of 51.32 Mbps at the maximum frequency of 236.574 MHz.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1457 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127441660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274005
C. Karfa
The designer sometimes wants to insert register(s) in specific location(s) of a design in order to break critical paths. To do so, the designer has to manually insert registers in all parallel paths as well to balance registers in all paths to keep the functionality of the design intact. This task is known as `register balancing' in the design community. The design size, complexity and hierarchy make manual register balancing in parallel paths task complex and error prone. The method presented here automatically inserts register(s) in the user specified location(s) and also automatically balances registers in all parallel paths. The register balancing problem has been suitably mapped to global retiming problem and solved using standard global retiming algorithm. The proposed method has been implemented in a model based high-level synthesis tool and tested on several Simulink designs.
{"title":"Automatic register balancing in model-based high-level synthesis","authors":"C. Karfa","doi":"10.1109/ACQED.2015.7274005","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274005","url":null,"abstract":"The designer sometimes wants to insert register(s) in specific location(s) of a design in order to break critical paths. To do so, the designer has to manually insert registers in all parallel paths as well to balance registers in all paths to keep the functionality of the design intact. This task is known as `register balancing' in the design community. The design size, complexity and hierarchy make manual register balancing in parallel paths task complex and error prone. The method presented here automatically inserts register(s) in the user specified location(s) and also automatically balances registers in all parallel paths. The register balancing problem has been suitably mapped to global retiming problem and solved using standard global retiming algorithm. The proposed method has been implemented in a model based high-level synthesis tool and tested on several Simulink designs.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130914706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7273999
A. Vatanjou, T. Ytterdal, S. Aunet
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.
{"title":"Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS","authors":"A. Vatanjou, T. Ytterdal, S. Aunet","doi":"10.1109/ACQED.2015.7273999","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7273999","url":null,"abstract":"This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131595738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274014
Fatemeh Banitorfian, F. Eshghabadi, Asrulnizam Abd Manaf, N. Noh, M. T. Mustaffa
This paper proposes a continuously-variable MEMS solenoid inductor with resonating frequency of over 8 GHz. This inductor allows high-tuning capability for resonance adjustment purpose in reconfigurable radio-frequency circuit devices. To achieve this goal, a channel is contrived to bypass the turns of the coil through the injection of a conductive liquid (here, Galinstan). Once the number of turns decreases, the inductance value falls according to the injection level. The proposed solenoid inductor is simulated using a full-wave three-dimensional electromagnetic analysis tool, HFSS, for silicon substrate with copper metallic coil for different level of conductive liquid injection. Beside the cost-effective and easy manufacturing process, the simulation results demonstrate the 150% tuning range. The EM simulation results show a maximum quality factor of 85 at 3 GHz for proposed inductor. The minimum and maximum inductance values are 1.5 and 4 nH at 4 GHz for low-resistivity Silicon. This tunable inductor can be applied into reconfigurable radio-frequency circuits and matching networks to tune the operating frequency of the system.
{"title":"Radio-frequency silicon-based CMOS-compatible MEMS variable solenoid micro-fluidic inductor with Galinstan-based continuously-adjustable turn-ratio technique","authors":"Fatemeh Banitorfian, F. Eshghabadi, Asrulnizam Abd Manaf, N. Noh, M. T. Mustaffa","doi":"10.1109/ACQED.2015.7274014","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274014","url":null,"abstract":"This paper proposes a continuously-variable MEMS solenoid inductor with resonating frequency of over 8 GHz. This inductor allows high-tuning capability for resonance adjustment purpose in reconfigurable radio-frequency circuit devices. To achieve this goal, a channel is contrived to bypass the turns of the coil through the injection of a conductive liquid (here, Galinstan). Once the number of turns decreases, the inductance value falls according to the injection level. The proposed solenoid inductor is simulated using a full-wave three-dimensional electromagnetic analysis tool, HFSS, for silicon substrate with copper metallic coil for different level of conductive liquid injection. Beside the cost-effective and easy manufacturing process, the simulation results demonstrate the 150% tuning range. The EM simulation results show a maximum quality factor of 85 at 3 GHz for proposed inductor. The minimum and maximum inductance values are 1.5 and 4 nH at 4 GHz for low-resistivity Silicon. This tunable inductor can be applied into reconfigurable radio-frequency circuits and matching networks to tune the operating frequency of the system.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123475643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274017
Chao Deng, Yici Cai, Qiang Zhou, Zhuwei Chen
As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variations can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations. By analyzing the influence of process variations on wire delay and buffer delay, we make a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations. The number and size of buffers on some critical paths are rearranged to reduce the skew results under process variations. Experiment results which are evaluated on ISPD 2010 benchmarks show that our algorithm achieves a significant 58% reduction on worst skew with only 6% increase on power consumption.
{"title":"An efficient buffer sizing algorithm for clock trees considering process variations","authors":"Chao Deng, Yici Cai, Qiang Zhou, Zhuwei Chen","doi":"10.1109/ACQED.2015.7274017","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274017","url":null,"abstract":"As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variations can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations. By analyzing the influence of process variations on wire delay and buffer delay, we make a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations. The number and size of buffers on some critical paths are rearranged to reduce the skew results under process variations. Experiment results which are evaluated on ISPD 2010 benchmarks show that our algorithm achieves a significant 58% reduction on worst skew with only 6% increase on power consumption.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-21DOI: 10.1109/ACQED.2015.7274022
Tsung-Chu Huang
As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.
{"title":"Cluster error correction and on-line repair for real-time TSV array","authors":"Tsung-Chu Huang","doi":"10.1109/ACQED.2015.7274022","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274022","url":null,"abstract":"As a high-speed circuit-level real-time channel through-silicon vias admit only several levels of logic gates for correcting and repairing within a clock cycle. Unfortunately they are usually arranged as a crowded array for floorplanning and manufacturing reasons. To repair cluster faults and correct cluster errors, in this paper a complete strategy with a fast and adaptive architecture is proposed for built-in self-repairing, correcting and monitoring. The strategy includes off-line built-in self-test/repair and on-line correction, monitoring and repair. An LFSR-based noisy channel emulator is developed for verifying the architecture and evaluating the performance in a magnified probabilistic model. A conditional probability based cluster error model is also developed for analyzing the MTTR and BLER analyses posteriori to the AWGN noise. Evaluations prove that the proposed architecture can be effectively and efficiently suitable for hybrid memory cube to test, repair, detect, correct and monitor a large cluster error almost within a nano-second.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122805010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-06DOI: 10.1109/ACQED.2015.7274011
H. Kerkhoff, Hassan Ebrahimi
In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extremely costly affair. The rare occurrences and short bursts of these faults are the most difficult ones to detect and diagnose in the testing arena. Several techniques are now being developed in ICs by us to cope with one particular category of NFFs, being the intermittent resistive faults (IRF). The reuse of these (on-chip) embedded instruments for detection of these faults at the board-level has been investigated in conjunction with the possibilities of enhancing the (mixed-signal) boundary-scan standard IEEE 1149.4. This paper will explore how this can be accomplished.
{"title":"Detection of intermittent resistive faults in electronic systems based on the mixed-signal boundary-scan standard","authors":"H. Kerkhoff, Hassan Ebrahimi","doi":"10.1109/ACQED.2015.7274011","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274011","url":null,"abstract":"In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extremely costly affair. The rare occurrences and short bursts of these faults are the most difficult ones to detect and diagnose in the testing arena. Several techniques are now being developed in ICs by us to cope with one particular category of NFFs, being the intermittent resistive faults (IRF). The reuse of these (on-chip) embedded instruments for detection of these faults at the board-level has been investigated in conjunction with the possibilities of enhancing the (mixed-signal) boundary-scan standard IEEE 1149.4. This paper will explore how this can be accomplished.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/ACQED.2015.7274030
F. Eshghabadi, Fatemeh Banitorfian, N. Noh, M. T. Mustaffa, Asrulnizam Abd Manaf
A fully hybrid computer-aided circuit design to achieve a first-pass on-board CMOS LNA fabrication is studied. The LNA is implemented in 0.13-μm CMOS process. A post-layout die-level electromagnetic-field analysis, to extract the interconnection and interaction parasitic between on-chip components, is used. The extracted touchstone model is integrated with circuit model of board including the microstrip lines and surface-mounted passive elements as well as the electromagnetic-field extracted model of radio-frequency coaxial connectors. The hybrid electromagnetic-circuit simulation results are compared with the measurement results for evaluation. The comparison presented an excellent correlation between the simulated and measured results. The connector's effects can be de-embedded using its developed electromagnetic model. This method of simulation and optimization is targeted to achieve first-pass run instead of optimization using costly prototypes.
{"title":"Fully-hybrid computer-aided RF LNA design and evaluation for GSM-1900 standard band","authors":"F. Eshghabadi, Fatemeh Banitorfian, N. Noh, M. T. Mustaffa, Asrulnizam Abd Manaf","doi":"10.1109/ACQED.2015.7274030","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274030","url":null,"abstract":"A fully hybrid computer-aided circuit design to achieve a first-pass on-board CMOS LNA fabrication is studied. The LNA is implemented in 0.13-μm CMOS process. A post-layout die-level electromagnetic-field analysis, to extract the interconnection and interaction parasitic between on-chip components, is used. The extracted touchstone model is integrated with circuit model of board including the microstrip lines and surface-mounted passive elements as well as the electromagnetic-field extracted model of radio-frequency coaxial connectors. The hybrid electromagnetic-circuit simulation results are compared with the measurement results for evaluation. The comparison presented an excellent correlation between the simulated and measured results. The connector's effects can be de-embedded using its developed electromagnetic model. This method of simulation and optimization is targeted to achieve first-pass run instead of optimization using costly prototypes.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123054239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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