Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274010
F. Tan, Ming Dak Chai, Mohamad Shahrir bin Tamrin
Capacitance is very important in High Speed I/O power integrity network design. There are different form of capacitors being used on the High Speed I/O Power Integrity Network to ensure the performance of the circuit. In this paper, the effectiveness of MIM capacitance and MOS capacitance is compared. MIM capacitance comes in bulk quantity but placed further away from the HSIO circuits. While MOS capacitance comes in considerably lower quantity but placed closer to the HSIO circuits. As such, there is a performance trade-off during the power integrity design considering the two different capacitances. While MOS capacitance is the preferred choice, the introduction of MIM capacitance has become an attractive option; as it offers much more capacitance at lower price. Can MOS capacitance be replaced by the MIM capacitance? The discussion will focus on PDN analysis to describe the change in behavior and the validation results to show the gap when MIM capacitance is completely removed.
{"title":"MIM capacitance efficiency study for high speed I/O power integrity network design: MIM and MIMless high speed I/O performance characterization","authors":"F. Tan, Ming Dak Chai, Mohamad Shahrir bin Tamrin","doi":"10.1109/ACQED.2015.7274010","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274010","url":null,"abstract":"Capacitance is very important in High Speed I/O power integrity network design. There are different form of capacitors being used on the High Speed I/O Power Integrity Network to ensure the performance of the circuit. In this paper, the effectiveness of MIM capacitance and MOS capacitance is compared. MIM capacitance comes in bulk quantity but placed further away from the HSIO circuits. While MOS capacitance comes in considerably lower quantity but placed closer to the HSIO circuits. As such, there is a performance trade-off during the power integrity design considering the two different capacitances. While MOS capacitance is the preferred choice, the introduction of MIM capacitance has become an attractive option; as it offers much more capacitance at lower price. Can MOS capacitance be replaced by the MIM capacitance? The discussion will focus on PDN analysis to describe the change in behavior and the validation results to show the gap when MIM capacitance is completely removed.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274008
Tanusree Kaibartta, C. Giri, H. Rahaman, D. K. Das
System-on-a-chip (SOC) uses embedded cores that require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach can be used for testing of three dimensional stacked integrated circuits (SICs) based on through-silicon vias (TSVs). Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using TSVs technology and present genetic algorithm for minimizing the post bond test time for 3D SICs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into different groups and places the cores of these groups in different layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.
{"title":"Optimizing test time for core-based 3-D integrated circuits by genetic algorithm","authors":"Tanusree Kaibartta, C. Giri, H. Rahaman, D. K. Das","doi":"10.1109/ACQED.2015.7274008","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274008","url":null,"abstract":"System-on-a-chip (SOC) uses embedded cores that require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach can be used for testing of three dimensional stacked integrated circuits (SICs) based on through-silicon vias (TSVs). Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using TSVs technology and present genetic algorithm for minimizing the post bond test time for 3D SICs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into different groups and places the cores of these groups in different layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133647964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274015
W. Zhong, N. Noh, B. A. Rosdi
Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort. Furthermore, the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment still lacks the capability to completely comprehend the checking of clock gating logics correctness. To address this, a verification method, called Clock Gating Assertion Check (CGAC) method, independent of verification environment is proposed aiming at achieving a faster pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow using codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design as the main inputs to generate checks at possible clock gating boundary conditions. The CGAC method was used to verify the clock gating logics of an existing Soft Intellectual Property (SIP) design. The implementation details of the method are discussed in this paper. By using the method, a total of 4 clock gating bugs were found and analysis on the impacts of the bugs is discussed. As a conclusion, the proposed method is proven effective in ensuring the correct clock gating implementation in a design.
{"title":"Clock gating assertion check: An approach towards achieving faster verification closure on clock gating functionality","authors":"W. Zhong, N. Noh, B. A. Rosdi","doi":"10.1109/ACQED.2015.7274015","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274015","url":null,"abstract":"Clock gating is a power reduction technique widely used in Register Transfer Level (RTL) stage of a chip design. The addition of clock gating logics has increased the complexity of a design and therefore requires considerable amount of verification effort. Furthermore, the scoreboard checking mechanism in Open Verification Methodology (OVM) verification environment still lacks the capability to completely comprehend the checking of clock gating logics correctness. To address this, a verification method, called Clock Gating Assertion Check (CGAC) method, independent of verification environment is proposed aiming at achieving a faster pre-silicon verification closure on clock gating logics with minimum verification effort. The proposed method is an automated flow using codes written in Hardware Description Language (HDL) in RTL stage and clock domains information of a design as the main inputs to generate checks at possible clock gating boundary conditions. The CGAC method was used to verify the clock gating logics of an existing Soft Intellectual Property (SIP) design. The implementation details of the method are discussed in this paper. By using the method, a total of 4 clock gating bugs were found and analysis on the impacts of the bugs is discussed. As a conclusion, the proposed method is proven effective in ensuring the correct clock gating implementation in a design.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121611041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274031
Shourya Kansal, A. Mantha, Y. B. Priyamvada, G. Chowdary, S. G. Singh, A. Dutta
This paper presents design of an improved start-up circuit for a micro scale solar energy harvesting system. A wide input voltage range (270mV - 1.8V) start-up circuit that can work in strong as well as weak illumination levels without causing any stress and reliability issues to the CMOS devices has been proposed. The use of native device (zero-Vth) and ultra-low power Band-gap Reference (BGR) helps to operate the start-up circuit within 1.8V maximum voltage allowed by 40nm CMOS technology. The complete system works with minimum power of 2.841μW at 270mV in start-up mode and works with minimum voltage of 100mV once the system enters into main converter mode. The system uses fractional open circuit voltage method (FOCV) to extract maximum power from solar cell when operating in main converter mode.
{"title":"A wide input voltage range start-up circuit for solar energy harvesting system","authors":"Shourya Kansal, A. Mantha, Y. B. Priyamvada, G. Chowdary, S. G. Singh, A. Dutta","doi":"10.1109/ACQED.2015.7274031","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274031","url":null,"abstract":"This paper presents design of an improved start-up circuit for a micro scale solar energy harvesting system. A wide input voltage range (270mV - 1.8V) start-up circuit that can work in strong as well as weak illumination levels without causing any stress and reliability issues to the CMOS devices has been proposed. The use of native device (zero-Vth) and ultra-low power Band-gap Reference (BGR) helps to operate the start-up circuit within 1.8V maximum voltage allowed by 40nm CMOS technology. The complete system works with minimum power of 2.841μW at 270mV in start-up mode and works with minimum voltage of 100mV once the system enters into main converter mode. The system uses fractional open circuit voltage method (FOCV) to extract maximum power from solar cell when operating in main converter mode.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114332785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274019
Quan Zhou, Xueyan Wang, Zhongdong Qi, Zhuwei Chen, Qiang Zhou, Yici Cai
Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.
{"title":"An accurate detailed routing routability prediction model in placement","authors":"Quan Zhou, Xueyan Wang, Zhongdong Qi, Zhuwei Chen, Qiang Zhou, Yici Cai","doi":"10.1109/ACQED.2015.7274019","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274019","url":null,"abstract":"Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult due to the complexity and uncertainty of routing. In this paper, we propose a new detailed routing routability prediction model based on supervised learning. After extracting key features in placement and detailed routing, multivariate adaptive regression is performed to train the connection between these two stages. Using a well-trained model, most design rule violations after detailed routing can be foreseen in placement stage. Experiments show that our average prediction accuracy is 79.8%, which is comparable with other state-of-art routability estimation techniques.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130044024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274006
Sharad Sinha, Wei Zhang
Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user has the flexibility to specify number of nodes and set node attributes like node type (operation type), in-degree and the maximum and the minimum parallelism in each control step. The generated dataflow graphs can be used for research in scheduling, allocation and hardware binding. Sharing of input parameters among researchers will allow generation of identical synthetic graphs on identical platforms thus facilitating easier and more meaningful comparison of results. The concept of "Biased Dataflow Graphs (BDFG)" is introduced where operations of certain types are large in number. These provide the required granularity in operations, exploitation of inherent parallelism and option to explore the area space in modern FPGAs consisting of LUTs, BRAMs and DSP slices. The generated graphs overcome these limitations in the two existing methods: Task Graphs for Free (TGFF) and Synchronous Dataflow Graphs for Free (SDF3).
{"title":"SynDFG: Synthetic dataflow graph generator for high-level synthesis","authors":"Sharad Sinha, Wei Zhang","doi":"10.1109/ACQED.2015.7274006","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274006","url":null,"abstract":"Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user has the flexibility to specify number of nodes and set node attributes like node type (operation type), in-degree and the maximum and the minimum parallelism in each control step. The generated dataflow graphs can be used for research in scheduling, allocation and hardware binding. Sharing of input parameters among researchers will allow generation of identical synthetic graphs on identical platforms thus facilitating easier and more meaningful comparison of results. The concept of \"Biased Dataflow Graphs (BDFG)\" is introduced where operations of certain types are large in number. These provide the required granularity in operations, exploitation of inherent parallelism and option to explore the area space in modern FPGAs consisting of LUTs, BRAMs and DSP slices. The generated graphs overcome these limitations in the two existing methods: Task Graphs for Free (TGFF) and Synchronous Dataflow Graphs for Free (SDF3).","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122743247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274007
Ahilan Appathurai, P. Deepa
The scaling down of semiconductor technology in FPGA increases the soft errors due to radiation effects in space. To address this technological challenge a novel coding technique, Counter Matrix Code (CMC) is proposed to protect the SRAM based FPGA's configuration memories (FCM) against radiation induced Multiple Bit Upsets (MBU) with Low cost and maximum correction capability. The proposed CMC is experimentally studied for its efficiency and reliability. The proposed technique improves the reliability of the memory by more than 7× compared to traditional HC technique and more than 4× compared to MC and more than 2× compared to DMC. The cost of the proposed work is less than traditional DMC and MC.
{"title":"Design for reliablity: A novel counter matrix code for FPGA based quality applications","authors":"Ahilan Appathurai, P. Deepa","doi":"10.1109/ACQED.2015.7274007","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274007","url":null,"abstract":"The scaling down of semiconductor technology in FPGA increases the soft errors due to radiation effects in space. To address this technological challenge a novel coding technique, Counter Matrix Code (CMC) is proposed to protect the SRAM based FPGA's configuration memories (FCM) against radiation induced Multiple Bit Upsets (MBU) with Low cost and maximum correction capability. The proposed CMC is experimentally studied for its efficiency and reliability. The proposed technique improves the reliability of the memory by more than 7× compared to traditional HC technique and more than 4× compared to MC and more than 2× compared to DMC. The cost of the proposed work is less than traditional DMC and MC.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126805714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274004
T. Adiono, Nur Ahmadi, Antonius P. Renardy, A. Fadila, Naufal Shidqi
COordinate Rotation DIgital Computer (CORDIC), is an algorithm that is used to perform trigonometric-related calculations. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of CORDIC algorithm using pipelined architecture. The pipelined CORDIC is then used in an all-digital FM modulator-demodulator. All designs are implemented in Verilog and synthesized by using Altera Quartus software with DE2-70 FPGA target board. The proposed design consumes 1,103 logic element, latency 33.32 ns, and maximum frequency 420.17 MHz. The overall system including FM modulator-demodulator utilizes 3,911 logic elements, latency 233.33 ns, and maximum frequency 60 MHz.
{"title":"A pipelined CORDIC architecture and its implementation in all-digital FM modulator-demodulator","authors":"T. Adiono, Nur Ahmadi, Antonius P. Renardy, A. Fadila, Naufal Shidqi","doi":"10.1109/ACQED.2015.7274004","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274004","url":null,"abstract":"COordinate Rotation DIgital Computer (CORDIC), is an algorithm that is used to perform trigonometric-related calculations. CORDIC is often utilized in the absence of hardware multiplier since this algorithm requires only addition, subtraction, bit shifting, and lookup table. This paper provides an implementation of CORDIC algorithm using pipelined architecture. The pipelined CORDIC is then used in an all-digital FM modulator-demodulator. All designs are implemented in Verilog and synthesized by using Altera Quartus software with DE2-70 FPGA target board. The proposed design consumes 1,103 logic element, latency 33.32 ns, and maximum frequency 420.17 MHz. The overall system including FM modulator-demodulator utilizes 3,911 logic elements, latency 233.33 ns, and maximum frequency 60 MHz.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274003
Z. Wang, Hui Xie, S. Chafekar, A. Chattopadhyay
Reliability has emerged as an important design criterion due to shrinking device dimensions. To address this challenge, researchers have proposed techniques compromising the Quality-of-Service across all design abstractions. Performing cross-layer reliability-QoS trade-off is a major challenge, which requires strong understanding of the fault propagation through different design abstractions. In this paper, we propose an analytical error prediction framework, based on probabilistic error masking matrices. The prediction is performed by propagating erroneous tokens through abstract logic networks. We report detailed experiments using a RISC processor and several embedded applications. The proposed approach demonstrates significantly faster reliability evaluation compared to pure simulation-driven approach, while predicts the erroneous effects of injected faults in both architecture and application levels. Several novel techniques are also proposed to increase the accuracy of error prediction.
{"title":"Architectural error prediction using probabilistic error masking matrices","authors":"Z. Wang, Hui Xie, S. Chafekar, A. Chattopadhyay","doi":"10.1109/ACQED.2015.7274003","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274003","url":null,"abstract":"Reliability has emerged as an important design criterion due to shrinking device dimensions. To address this challenge, researchers have proposed techniques compromising the Quality-of-Service across all design abstractions. Performing cross-layer reliability-QoS trade-off is a major challenge, which requires strong understanding of the fault propagation through different design abstractions. In this paper, we propose an analytical error prediction framework, based on probabilistic error masking matrices. The prediction is performed by propagating erroneous tokens through abstract logic networks. We report detailed experiments using a RISC processor and several embedded applications. The proposed approach demonstrates significantly faster reliability evaluation compared to pure simulation-driven approach, while predicts the erroneous effects of injected faults in both architecture and application levels. Several novel techniques are also proposed to increase the accuracy of error prediction.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127532277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-24DOI: 10.1109/ACQED.2015.7274032
M. A. Sheikh, N. Ali, N. H. Hamid, F. Hussin, V. Shukla
Reliability of digital microfluidic biochips (DMFB) emerges to be a critical issue, as they are becoming a popular alternative for laboratory experiments like DNA analysis, immunoassays and safety critical clinical diagnostics. To improve DMFB reliability, the key is to know the possible points of failure of its electrode cells. In this paper, a novel test methodology is introduced to monitor the health of the DMFB by classifying its individual cells into weak, faulty and fault-free. The emphasis is on identifying physically degraded cells in the DMFB array and reducing their over-use, thus saving those cells from becoming faulty during operation. Degradation in cell health is measured by the change in its capacitance via a capacitance measurement circuit that can be integrated with the DMFB. The paper also presents the circuit to classify the cells as weak, faulty and fault free, implemented using 180nm technology.
{"title":"On enhancing the reliability of digital microfluidic biochips (DMFB) through electrode cells health classification","authors":"M. A. Sheikh, N. Ali, N. H. Hamid, F. Hussin, V. Shukla","doi":"10.1109/ACQED.2015.7274032","DOIUrl":"https://doi.org/10.1109/ACQED.2015.7274032","url":null,"abstract":"Reliability of digital microfluidic biochips (DMFB) emerges to be a critical issue, as they are becoming a popular alternative for laboratory experiments like DNA analysis, immunoassays and safety critical clinical diagnostics. To improve DMFB reliability, the key is to know the possible points of failure of its electrode cells. In this paper, a novel test methodology is introduced to monitor the health of the DMFB by classifying its individual cells into weak, faulty and fault-free. The emphasis is on identifying physically degraded cells in the DMFB array and reducing their over-use, thus saving those cells from becoming faulty during operation. Degradation in cell health is measured by the change in its capacitance via a capacitance measurement circuit that can be integrated with the DMFB. The paper also presents the circuit to classify the cells as weak, faulty and fault free, implemented using 180nm technology.","PeriodicalId":376857,"journal":{"name":"2015 6th Asia Symposium on Quality Electronic Design (ASQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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