The status of GaAs monolithic microwave integrated circuits (MMICs), technological trends and several current developments in Japan are described, mainly from the point of view of circuit technology and applications. Several commercial applications for GaAs MMICs are now envisioned. Research and development in Japan is mainly for commercial applications, in contrast to the US MMIC Program for military MMIC use. Work on frequency dividers, low-noise amplifier components, and both high-power and nonlinear circuits is summarized. Several MMIC circuit technologies under development such as a 30-GHz satellite transponder, a 26-GHz uniplanar receiver and a 12-GHz broadcast satellite converter are noted. It is projected that: (1) a MMIC direct-broadcast satellite (DBS) low-noise converter could be ready for production and available in 1-2 years (from 1989); (2) MMIC modules (using microstrip structure or uniplanar structure) that operate at high frequencies could be achieved in communication systems.<>
{"title":"MMIC progress in Japan","authors":"M. Aikawa, H. Ogawa, T. Sugeta","doi":"10.1109/MCS.1989.37249","DOIUrl":"https://doi.org/10.1109/MCS.1989.37249","url":null,"abstract":"The status of GaAs monolithic microwave integrated circuits (MMICs), technological trends and several current developments in Japan are described, mainly from the point of view of circuit technology and applications. Several commercial applications for GaAs MMICs are now envisioned. Research and development in Japan is mainly for commercial applications, in contrast to the US MMIC Program for military MMIC use. Work on frequency dividers, low-noise amplifier components, and both high-power and nonlinear circuits is summarized. Several MMIC circuit technologies under development such as a 30-GHz satellite transponder, a 26-GHz uniplanar receiver and a 12-GHz broadcast satellite converter are noted. It is projected that: (1) a MMIC direct-broadcast satellite (DBS) low-noise converter could be ready for production and available in 1-2 years (from 1989); (2) MMIC modules (using microstrip structure or uniplanar structure) that operate at high frequencies could be achieved in communication systems.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design, fabrication, and performance of monolithic microwave integrated circuit single-pole single-throw (MMIC SPST) and single-pole double-throw (SPDT) switches with on-chip transistor-transistor logic (TTL) compatible drivers is presented. Both switch types cover 1-20 GHz, operate from a single +10 to +12 V power supply and commute in less than 15 ns. Both have at least -12 dB return loss at all ports and handle +22 dBm signal levels. The SPST switch has an insertion loss of 2.5 dB and >50 dB isolation. The SPDT switch's insertion loss is 2.7 dB with 49 dB isolation. The switches require only external DC blocking capacitors to set the lower end of their useful bandwidth. The excellent isolation achieved by these switches is principally attributable to the design of the series and shunt FETs used in their realization.<>
{"title":"High isolation 1-20 GHz MMIC switches with on-chip drivers","authors":"J. Eisenberg, T. B. Chamberlain, L. Sloan","doi":"10.1109/MCS.1989.37259","DOIUrl":"https://doi.org/10.1109/MCS.1989.37259","url":null,"abstract":"The design, fabrication, and performance of monolithic microwave integrated circuit single-pole single-throw (MMIC SPST) and single-pole double-throw (SPDT) switches with on-chip transistor-transistor logic (TTL) compatible drivers is presented. Both switch types cover 1-20 GHz, operate from a single +10 to +12 V power supply and commute in less than 15 ns. Both have at least -12 dB return loss at all ports and handle +22 dBm signal levels. The SPST switch has an insertion loss of 2.5 dB and >50 dB isolation. The SPDT switch's insertion loss is 2.7 dB with 49 dB isolation. The switches require only external DC blocking capacitors to set the lower end of their useful bandwidth. The excellent isolation achieved by these switches is principally attributable to the design of the series and shunt FETs used in their realization.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126020225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors describe the technology development leading to a family of high-electron-mobility transistor (HEMT) monolithic low-noise amplifiers (LNAs), and present modeled and measured performance data on LNAs covering the 2-20 GHz frequency band. These amplifiers achieve noise figures comparable to their counterpart in hybrid HEMT technology. The amplifiers are configured in a cascadable design, with simultaneous low input and output VSWR, and flat gain response. Performance results include measured and modeled data for a 2-7 GHz LNA with 2.5-dB noise figure, a 2-20-GHz distributed amplifier with 9.5-dB flat gain and 3.5-dB noise figure, and a 5-11-GHz and >3.5 balanced LNA with 10-dB gain and <2.5-dB noise figure (6-11 GHz). A preliminary temperature step-stress reliability evaluation on the discrete-process HEMT device is also presented.<>
{"title":"A family of 2-20 GHz broadband low noise AlGaAs HEMT MMIC amplifiers","authors":"R. Dixit, B. Nelson, W. Jones, J. Carillo","doi":"10.1109/MCS.1989.37253","DOIUrl":"https://doi.org/10.1109/MCS.1989.37253","url":null,"abstract":"The authors describe the technology development leading to a family of high-electron-mobility transistor (HEMT) monolithic low-noise amplifiers (LNAs), and present modeled and measured performance data on LNAs covering the 2-20 GHz frequency band. These amplifiers achieve noise figures comparable to their counterpart in hybrid HEMT technology. The amplifiers are configured in a cascadable design, with simultaneous low input and output VSWR, and flat gain response. Performance results include measured and modeled data for a 2-7 GHz LNA with 2.5-dB noise figure, a 2-20-GHz distributed amplifier with 9.5-dB flat gain and 3.5-dB noise figure, and a 5-11-GHz and >3.5 balanced LNA with 10-dB gain and <2.5-dB noise figure (6-11 GHz). A preliminary temperature step-stress reliability evaluation on the discrete-process HEMT device is also presented.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of a Ka-band monolithic GaAs two-stage power amplifier with 3.6-mm total gate width is presented. The monolithic amplifier uses FETs with 1.2-mm and 2.4-mm gate widths for the first-stage and second-stage devices, respectively. It delivers an output power of 0.56 W, with a power gain of 7.2 dB, and a power-added efficiency of 15% at 28 GHz. Output power of more than 0.5 W is obtained over 27.5-28.5 GHz, with power gain exceeding 5 dB. The authors expect that further improvements in output power will be achieved through drain current optimization and a monolithic parallel combining of amplifiers.<>
{"title":"Ka-band monolithic GaAs two-stage power amplifier","authors":"Y. Oda, T. Yoshida, K. Kai, S. Arai, S. Yanagawa","doi":"10.1109/MCS.1989.37257","DOIUrl":"https://doi.org/10.1109/MCS.1989.37257","url":null,"abstract":"The development of a Ka-band monolithic GaAs two-stage power amplifier with 3.6-mm total gate width is presented. The monolithic amplifier uses FETs with 1.2-mm and 2.4-mm gate widths for the first-stage and second-stage devices, respectively. It delivers an output power of 0.56 W, with a power gain of 7.2 dB, and a power-added efficiency of 15% at 28 GHz. Output power of more than 0.5 W is obtained over 27.5-28.5 GHz, with power gain exceeding 5 dB. The authors expect that further improvements in output power will be achieved through drain current optimization and a monolithic parallel combining of amplifiers.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125605805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Avasarala, D. Day, S. Chan, C. Hua, J. R. Basset
The design and performance of a two-stage molecular-beam epitaxy (MBE) monolithic power amplifier chip is presented. The monolithic chip contains full interstage matching, partial matching at the input, and no match at the output. When matched to 50 Omega at input and output using off-chip circuitry, the MMIC demonstrates an overall performance of 34 dBm (0.436 W/mm) of power, 36% of power-added efficiency (PAE), and 14.5 dB of associated gain across the band 9.0-10.0 GHz. The PAE was as high as 38% in parts of the band. The average performance of 26 devices from at least 12 wafers from 5 different runs is 33.6 dBm (0.4 W/mm), 32%, and 14 dB, respectively. The chip size is 0.081 in*0.070 in*0.003 in (2.06 mm*1.78 mm/sup 2/).<>
{"title":"A 2.5-watt high frequency X-band power MMIC","authors":"M. Avasarala, D. Day, S. Chan, C. Hua, J. R. Basset","doi":"10.1109/MCS.1989.37255","DOIUrl":"https://doi.org/10.1109/MCS.1989.37255","url":null,"abstract":"The design and performance of a two-stage molecular-beam epitaxy (MBE) monolithic power amplifier chip is presented. The monolithic chip contains full interstage matching, partial matching at the input, and no match at the output. When matched to 50 Omega at input and output using off-chip circuitry, the MMIC demonstrates an overall performance of 34 dBm (0.436 W/mm) of power, 36% of power-added efficiency (PAE), and 14.5 dB of associated gain across the band 9.0-10.0 GHz. The PAE was as high as 38% in parts of the band. The average performance of 26 devices from at least 12 wafers from 5 different runs is 33.6 dBm (0.4 W/mm), 32%, and 14 dB, respectively. The chip size is 0.081 in*0.070 in*0.003 in (2.06 mm*1.78 mm/sup 2/).<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Boire, G. St. Onge, C. Barratt, G. Norris, A. Moysenko
Five-bit monolithic microwave integrated circuits (MMIC) phase shifters that cover over two octaves of bandwidth are developed for functions such as electronic beamsteering and frequency translation. The authors describe two digitally controlled MMIC phase shifters optimized for different operating bandwidths. A lowband version of the phase shifter is designed for the 2.0-6.0-GHz frequency range, and a highband version is designed for the 4.5-18.0-GHz frequency range. Both versions maintain useful performance levels significantly beyond their design bandwidths. The typical measured circuit performance of a highband phase shifter chip in the 4.5-18-GHz band shows a maximum phase error of less than 20 degrees and a +or-1.15-dB maximum change in insertion loss with phase state. The measured circuit performance of a lowband phase shifter chip in the 2.0-6.0-GHz band shows a maximum phase error of less than 15 degrees and less than +or-0.6-dB insertion loss variation with phase state.<>
{"title":"4:1 bandwidth digital five bit MMIC phase shifters","authors":"D. Boire, G. St. Onge, C. Barratt, G. Norris, A. Moysenko","doi":"10.1109/MCS.1989.37265","DOIUrl":"https://doi.org/10.1109/MCS.1989.37265","url":null,"abstract":"Five-bit monolithic microwave integrated circuits (MMIC) phase shifters that cover over two octaves of bandwidth are developed for functions such as electronic beamsteering and frequency translation. The authors describe two digitally controlled MMIC phase shifters optimized for different operating bandwidths. A lowband version of the phase shifter is designed for the 2.0-6.0-GHz frequency range, and a highband version is designed for the 4.5-18.0-GHz frequency range. Both versions maintain useful performance levels significantly beyond their design bandwidths. The typical measured circuit performance of a highband phase shifter chip in the 4.5-18-GHz band shows a maximum phase error of less than 20 degrees and a +or-1.15-dB maximum change in insertion loss with phase state. The measured circuit performance of a lowband phase shifter chip in the 2.0-6.0-GHz band shows a maximum phase error of less than 15 degrees and less than +or-0.6-dB insertion loss variation with phase state.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"693 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Coget, P. Philippe, V. Pauker, P. Dautriche, P. Jean
A 0.1-4.5-GHz GaAs monolithic quadrature phase shifter with very small phase error, based on a phase-locked loop system, was designed, fabricated, and tested. The phase shifter consists of two RC all-pass networks with FETs used as voltage-controlled resistors. It delivers four quadrature output signals as required for the operation of the double balanced mixers used in the receiver. The main feature of this system is that it has an overall phase error of less than 2 degrees . When integrated in a broadband receiver the system produced an image rejection of at least 30 dB over the 0.1-4.5-GHz frequency band.<>
{"title":"A multioctave active MMIC quadrature phase shifter","authors":"P. Coget, P. Philippe, V. Pauker, P. Dautriche, P. Jean","doi":"10.1109/MCS.1989.37266","DOIUrl":"https://doi.org/10.1109/MCS.1989.37266","url":null,"abstract":"A 0.1-4.5-GHz GaAs monolithic quadrature phase shifter with very small phase error, based on a phase-locked loop system, was designed, fabricated, and tested. The phase shifter consists of two RC all-pass networks with FETs used as voltage-controlled resistors. It delivers four quadrature output signals as required for the operation of the double balanced mixers used in the receiver. The main feature of this system is that it has an overall phase error of less than 2 degrees . When integrated in a broadband receiver the system produced an image rejection of at least 30 dB over the 0.1-4.5-GHz frequency band.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130808427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A GaAs/AlGaAs heterojunction bipolar transistor (HBT) monolithic 5-bit digital gain control amplifier is presented that was developed for use in electronic warfare receivers. The digital-control variable-gain amplifier is composed of five gain/attenuation stages and an output buffer. A current-mode logic (CML) switch selects either the high-gain differential pair or the attenuating differential pair for each of the five stages. Distributing the gain into +or-16 dB, +or-8 dB, +or-4 dB, +or-2 dB, and +or-1 dB increments achieves +or-31 dB programmability in 2-dB increments from DC to 2.25 GHz, with less than 1.6 dB RMS gain error across the band. The switched gain amplifiers were fabricated with a 3- mu m-emitter, self-aligned base ohmic metal (SABM) HBT IC fabrication process. The chip consumes 1.3 W and measures 1.2 mm*2.2 mm.<>
提出了一种用于电子战接收机的GaAs/AlGaAs异质结双极晶体管(HBT)单片5位数字增益控制放大器。数字控制变增益放大器由五个增益/衰减级和一个输出缓冲器组成。电流模式逻辑(CML)开关为五个级中的每一级选择高增益差分对或衰减差分对。将增益分配到+或16 dB、+或8 dB、+或4 dB、+或2 dB和+或1 dB增量，实现了从DC到2.25 GHz的2 dB增量+或31 dB可编程性，整个频段的增益误差小于1.6 dB RMS。采用3 μ m发射极、自对准基极欧姆金属(SABM) HBT集成电路工艺制备了开关增益放大器。芯片功耗为1.3 W，尺寸为1.2 mm*2.2 mm
{"title":"A GaAs HBT monolithic microwave switched-gain amplifier with +31 dB to -31 dB gain in 2 dB increments","authors":"A. Oki, G. Gorman, J. Camou, D. Umemoto, M.E. Kim","doi":"10.1109/MCS.1989.37268","DOIUrl":"https://doi.org/10.1109/MCS.1989.37268","url":null,"abstract":"A GaAs/AlGaAs heterojunction bipolar transistor (HBT) monolithic 5-bit digital gain control amplifier is presented that was developed for use in electronic warfare receivers. The digital-control variable-gain amplifier is composed of five gain/attenuation stages and an output buffer. A current-mode logic (CML) switch selects either the high-gain differential pair or the attenuating differential pair for each of the five stages. Distributing the gain into +or-16 dB, +or-8 dB, +or-4 dB, +or-2 dB, and +or-1 dB increments achieves +or-31 dB programmability in 2-dB increments from DC to 2.25 GHz, with less than 1.6 dB RMS gain error across the band. The switched gain amplifiers were fabricated with a 3- mu m-emitter, self-aligned base ohmic metal (SABM) HBT IC fabrication process. The chip consumes 1.3 W and measures 1.2 mm*2.2 mm.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131492210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Bahl, R. Wang, A. Geissberger, E. Griffin, C. Andricos
The design and performance of a C-band single-chip GaAs monolithic microwave integrated circuit (MMIC) amplifier manufactured using a fully planar, refractory, self-aligned gate (SAG) technology is described. The design uses a 4-mm gate periphery FET with a unit finger width of 250 mu m as a standard cell. The power MMIC design is based on measured data for the FET, which has three source vias for low parasitic source grounding. The FET was optimized for maximum power and efficiency at C-band and has 16 fingers. The design uses an innovative method to determine accurate linear models for the power FET used to design the matching network and for simulating accurately the performance of the power amplifier. The amplifier demonstrates 10 W power output at 5.5 GHz with associated gain of 5 dB and power-added efficiency of 36%. The functional yield of the IC on the best wafer was 70%.<>
{"title":"C-band 10 Watt MMIC amplifier manufactured using refractory SAG process","authors":"I. Bahl, R. Wang, A. Geissberger, E. Griffin, C. Andricos","doi":"10.1109/MCS.1989.37254","DOIUrl":"https://doi.org/10.1109/MCS.1989.37254","url":null,"abstract":"The design and performance of a C-band single-chip GaAs monolithic microwave integrated circuit (MMIC) amplifier manufactured using a fully planar, refractory, self-aligned gate (SAG) technology is described. The design uses a 4-mm gate periphery FET with a unit finger width of 250 mu m as a standard cell. The power MMIC design is based on measured data for the FET, which has three source vias for low parasitic source grounding. The FET was optimized for maximum power and efficiency at C-band and has 16 fingers. The design uses an innovative method to determine accurate linear models for the power FET used to design the matching network and for simulating accurately the performance of the power amplifier. The amplifier demonstrates 10 W power output at 5.5 GHz with associated gain of 5 dB and power-added efficiency of 36%. The functional yield of the IC on the best wafer was 70%.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Bellantoni, D. Bartle, D. Payne, G. McDermott, S. Bandla, R. Tayrani, L. Raffaelli
A high-power Ka-band single-pole double-throw (SPDT) switch using monolithic GaAs epitaxial p-i-n diode technology is presented. The switch uses epitaxial vertical p-i-n diode structures in a shunt configuration optimized for low loss and high isolation under high power signal conditions. The vertical epitaxial structure provides lower RF impedance under forward bias and superior power handling capability. An additional feature of the circuit is the location of the p-i-n diode directly underneath the RF line, which improves isolation and increases bandwidth. Insertion loss is 0.7 dB at 35 GHz, and isolation is better than 32 dB from 30 to 40 GHz. The power-handling capability is at least +38 dBm pulsed and +35 dBm CW. Switching speed rise and fall times are 2 ns.<>
{"title":"A monolithic high power Ka-band PIN switch","authors":"J. Bellantoni, D. Bartle, D. Payne, G. McDermott, S. Bandla, R. Tayrani, L. Raffaelli","doi":"10.1109/MCS.1989.37260","DOIUrl":"https://doi.org/10.1109/MCS.1989.37260","url":null,"abstract":"A high-power Ka-band single-pole double-throw (SPDT) switch using monolithic GaAs epitaxial p-i-n diode technology is presented. The switch uses epitaxial vertical p-i-n diode structures in a shunt configuration optimized for low loss and high isolation under high power signal conditions. The vertical epitaxial structure provides lower RF impedance under forward bias and superior power handling capability. An additional feature of the circuit is the location of the p-i-n diode directly underneath the RF line, which improves isolation and increases bandwidth. Insertion loss is 0.7 dB at 35 GHz, and isolation is better than 32 dB from 30 to 40 GHz. The power-handling capability is at least +38 dBm pulsed and +35 dBm CW. Switching speed rise and fall times are 2 ns.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122431773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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