An accurate MESFET nonlinear model and a reliable model verification approach that uses the on-wafer RF probing method are presented. The nonlinear model is based on small-signal S-parameter characterization of the MESFET at a wide range of bias voltages and is capable of accurately predicting the MMIC amplifier performances at various bias voltages, frequencies, and input power levels (both small and large signals). A model verification scheme is used that was designed to eliminate many measurement uncertainties. In this approach, the nonlinear model is verified by comparing the simulation results of a single-stage MMIC amplifier with the measurement data. The S-parameters of the amplifier's input and output matching circuits are first accurately measured using the on-wafer RF probes. These data are then input to the simulation program for the complete amplifier simulation. Simulation results for a MMIC amplifier at various frequencies, bias voltages, and power levels agree well with the measurement data.<>
{"title":"Accurate nonlinear modeling and verification of MMIC amplifier","authors":"V. Hwang, Y. Shih, H. Le","doi":"10.1109/MCS.1989.37258","DOIUrl":"https://doi.org/10.1109/MCS.1989.37258","url":null,"abstract":"An accurate MESFET nonlinear model and a reliable model verification approach that uses the on-wafer RF probing method are presented. The nonlinear model is based on small-signal S-parameter characterization of the MESFET at a wide range of bias voltages and is capable of accurately predicting the MMIC amplifier performances at various bias voltages, frequencies, and input power levels (both small and large signals). A model verification scheme is used that was designed to eliminate many measurement uncertainties. In this approach, the nonlinear model is verified by comparing the simulation results of a single-stage MMIC amplifier with the measurement data. The S-parameters of the amplifier's input and output matching circuits are first accurately measured using the on-wafer RF probes. These data are then input to the simulation program for the complete amplifier simulation. Simulation results for a MMIC amplifier at various frequencies, bias voltages, and power levels agree well with the measurement data.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116837114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three stages of dual-gate FETs (DGFETs) are used to achieve greater than 1-W output power with more than 14 dB associated gain under compressed RF drive while providing more than 30 dB of gain control. Minimal phase variation over the gain control range was also demonstrated. The first, second, and third stages have 800, 3200, and 6400- mu m gate peripheries, respectively. The compressed gain of this amplifier is >14 dB with >1 W output power over the 13.5- to 15.5-GHz band. The input return loss is typically >15 dB across the band.<>
{"title":"Monolithic Ku-band GaAs 1-watt constant phase variable power amplifier","authors":"S. Pritchett","doi":"10.1109/MCS.1989.37256","DOIUrl":"https://doi.org/10.1109/MCS.1989.37256","url":null,"abstract":"Three stages of dual-gate FETs (DGFETs) are used to achieve greater than 1-W output power with more than 14 dB associated gain under compressed RF drive while providing more than 30 dB of gain control. Minimal phase variation over the gain control range was also demonstrated. The first, second, and third stages have 800, 3200, and 6400- mu m gate peripheries, respectively. The compressed gain of this amplifier is >14 dB with >1 W output power over the 13.5- to 15.5-GHz band. The input return loss is typically >15 dB across the band.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129563565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Adelseck, A. Colquhoun, J. Dieudonné, G. Ebert, J. Selders, K. Schmegner, W. Schwab
A method of simultaneously fabricating MESFETs with a maximum frequency of oscillation (f/sub max/) of 70 GHz and Schottky diodes with a gain-bandwidth product (f/sub T/) of approximately=2300 GHz to produce a 60-GHz mixer is given. A deep selective n/sup +/ implantation for a buried n/sup +/ zone under the mixer diode was used. Metalorganic chemical vapor deposition (MOCVD) was used for the growth of the active n layer and an n/sup +/ surface contact layer. The MESFETs and the diodes were both fabricated with a recessed Schottky contact structure using Ti-Pt-Au metallization. Arrays of 30 different diodes and 55 different MESFETs were fabricated to study the process technology and to get optimum devices for a receiver chip containing a diode balanced mixer plus a low-noise intermediate-frequency (IF) amplifier. The conversion loss and noise figures of the diodes were measured and compared with those obtained from computer simulations. Both large- and small-signal analysis are included. The 60-GHz balanced mixer chip shows a conversion loss of 6.0 dB and a double-sideband noise figure of 3.3 dB.<>
{"title":"A monolithic 60 GHz diode mixer in FET compatible technology","authors":"B. Adelseck, A. Colquhoun, J. Dieudonné, G. Ebert, J. Selders, K. Schmegner, W. Schwab","doi":"10.1109/MCS.1989.37270","DOIUrl":"https://doi.org/10.1109/MCS.1989.37270","url":null,"abstract":"A method of simultaneously fabricating MESFETs with a maximum frequency of oscillation (f/sub max/) of 70 GHz and Schottky diodes with a gain-bandwidth product (f/sub T/) of approximately=2300 GHz to produce a 60-GHz mixer is given. A deep selective n/sup +/ implantation for a buried n/sup +/ zone under the mixer diode was used. Metalorganic chemical vapor deposition (MOCVD) was used for the growth of the active n layer and an n/sup +/ surface contact layer. The MESFETs and the diodes were both fabricated with a recessed Schottky contact structure using Ti-Pt-Au metallization. Arrays of 30 different diodes and 55 different MESFETs were fabricated to study the process technology and to get optimum devices for a receiver chip containing a diode balanced mixer plus a low-noise intermediate-frequency (IF) amplifier. The conversion loss and noise figures of the diodes were measured and compared with those obtained from computer simulations. Both large- and small-signal analysis are included. The 60-GHz balanced mixer chip shows a conversion loss of 6.0 dB and a double-sideband noise figure of 3.3 dB.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129861740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A monolithic-switch FET (MFET) control device that can be integrated with other monolithic functions or used as a discrete component in a monolithic microwave integrated circuit (MMIC) structure is presented. The MFET device is a suitable replacement for p-i-n diodes as a generic control element in applications from 10 W to several hundred W CW, and has the advantages of a conventional GaAs switch FET (SFET). The increased power handling is due to the device's ability to overcome the breakdown voltage limitation of conventional SFETs. The design, fabrication, and performance of two high-power control components using MFET devices are described as examples of the implementation of this technology: an L-band terminated single-pole single-throw (SPST) switch, and an L-band limiter.<>
{"title":"High power control components using a new monolithic FET structure","authors":"M. Shifrin, P. Katzin, Y. Ayasli","doi":"10.1109/MCS.1989.37261","DOIUrl":"https://doi.org/10.1109/MCS.1989.37261","url":null,"abstract":"A monolithic-switch FET (MFET) control device that can be integrated with other monolithic functions or used as a discrete component in a monolithic microwave integrated circuit (MMIC) structure is presented. The MFET device is a suitable replacement for p-i-n diodes as a generic control element in applications from 10 W to several hundred W CW, and has the advantages of a conventional GaAs switch FET (SFET). The increased power handling is due to the device's ability to overcome the breakdown voltage limitation of conventional SFETs. The design, fabrication, and performance of two high-power control components using MFET devices are described as examples of the implementation of this technology: an L-band terminated single-pole single-throw (SPST) switch, and an L-band limiter.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128728510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A circuit topology is presented for realizing power dividers with bandwidths of 2.5:1 or greater on MMIC. This topology consists of lumped-element interconnected networks and is thus ideally suited for MMIC technology. This proposed minimum-element topology favors component values that are easily realizable and thus minimize losses due to low-Q elements. A three-way divider was fabricated that achieved 5.8-dB nominal insertion loss and 18-dB isolation form 4 to 10 GHz. The circuit was designed on a 60-mil*60-mil chip and included RF probe pads at each port to allow measurement of on-chip performance. all circuit components were realized as MIM capacitors. NiCr resistors, and air bridge inductors. A short length of high-impedance transmission line was included at the input on the divider to compensate for the parasitic nature of the lumped elements. Excellent agreement was obtained between measured and predicted performance.<>
{"title":"An ultra wide bandwidth power divider on MMIC operating 4 to 10 GHz","authors":"J. Staudinger","doi":"10.1109/MCS.1989.37278","DOIUrl":"https://doi.org/10.1109/MCS.1989.37278","url":null,"abstract":"A circuit topology is presented for realizing power dividers with bandwidths of 2.5:1 or greater on MMIC. This topology consists of lumped-element interconnected networks and is thus ideally suited for MMIC technology. This proposed minimum-element topology favors component values that are easily realizable and thus minimize losses due to low-Q elements. A three-way divider was fabricated that achieved 5.8-dB nominal insertion loss and 18-dB isolation form 4 to 10 GHz. The circuit was designed on a 60-mil*60-mil chip and included RF probe pads at each port to allow measurement of on-chip performance. all circuit components were realized as MIM capacitors. NiCr resistors, and air bridge inductors. A short length of high-impedance transmission line was included at the input on the divider to compensate for the parasitic nature of the lumped elements. Excellent agreement was obtained between measured and predicted performance.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127256936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ducourant, P. Philippe, P. Dautriche, V. Pauker, C. Villalon, M. Pertus, J.-P. Damour
A fully integrated three-chip VHF-UHF TV tuner system is presented that uses 0.7- mu m MESFET GaAs technology. The system, based on the double frequency conversion method, consists of an upconverter (IF/sub 1/=1.9 GHz), a smoothing filter, and an image rejection downconverter (IF/sub 2/=35 MHz) connected together on an alumina substrate. The total conversion gain is 30 dB and the rejection level is more than 60 dB throughout the VHF-UHF band with only one preliminary trimming at 500 MHz. Upconverter narrowband amplifier, image frequency rejection mixer (IFRM), and phase shifter measurements data are provided.<>
{"title":"A 3 chip GaAs double conversion TV tuner system with 70 dB image rejection","authors":"T. Ducourant, P. Philippe, P. Dautriche, V. Pauker, C. Villalon, M. Pertus, J.-P. Damour","doi":"10.1109/MCS.1989.37269","DOIUrl":"https://doi.org/10.1109/MCS.1989.37269","url":null,"abstract":"A fully integrated three-chip VHF-UHF TV tuner system is presented that uses 0.7- mu m MESFET GaAs technology. The system, based on the double frequency conversion method, consists of an upconverter (IF/sub 1/=1.9 GHz), a smoothing filter, and an image rejection downconverter (IF/sub 2/=35 MHz) connected together on an alumina substrate. The total conversion gain is 30 dB and the rejection level is more than 60 dB throughout the VHF-UHF band with only one preliminary trimming at 500 MHz. Upconverter narrowband amplifier, image frequency rejection mixer (IFRM), and phase shifter measurements data are provided.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123193000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Lan, J.C. Chen, C. Pao, M. I. Herman, R. Neidert
The authors report on the design, fabrication, and performance of several monolithic integrated circuits intended for use in a W-band (75 to 110 GHz) channelized monolithic receiver. The integrated circuits consist of a four-channel monolithic multiplexer, an ion-implanted W-band monolithic balanced mixer, a broadband low-noise intermediate-frequency IF amplifier, and a monolithic Gunn local oscillator. The integration of these circuits into a wideband monolithic receiver front-end using a four-channel downconverter chip and two dual-channel local oscillator chips is also discussed.<>
{"title":"A W-band channelized monolithic receiver","authors":"G. Lan, J.C. Chen, C. Pao, M. I. Herman, R. Neidert","doi":"10.1109/MCS.1989.37271","DOIUrl":"https://doi.org/10.1109/MCS.1989.37271","url":null,"abstract":"The authors report on the design, fabrication, and performance of several monolithic integrated circuits intended for use in a W-band (75 to 110 GHz) channelized monolithic receiver. The integrated circuits consist of a four-channel monolithic multiplexer, an ion-implanted W-band monolithic balanced mixer, a broadband low-noise intermediate-frequency IF amplifier, and a monolithic Gunn local oscillator. The integration of these circuits into a wideband monolithic receiver front-end using a four-channel downconverter chip and two dual-channel local oscillator chips is also discussed.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122940276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 2 to 18 GHz monolithic GaAs low-noise distributed amplifier with 10 dB nominal gain was designed and built using the standard Texas Instrument GaAs foundry process. This process incorporates ground vias, metal-insulator-metal (MIM) capacitors and air bridges. The amplifier uses 0.5- mu m-gate ion-implanted dual-gate FETs (DGFETs). The noise figure is less than 5.7 dB over the 2 to 18 GHz band and less than 4.0 dB from 3 to 13 GHz. The DGFET amplifier provides gain control capability; with 5 V and 60 mA operating bias it provides 10-dB nominal gain, input return loss better than 10 dB, and output return loss better than 8 dB. Lower power consumption was demonstrated at 5 V and 30 mA. With this reduced bias the nominal gain drops to 8 dB and the noise figure degrades by 0.3 dB. Increasing the bias to 7 V and 90 mA increases the nominal gain to 11 dB while degrading the noise figure by 0.3 dB. This increased bias gives the amplifier medium power capability, with a 1-dB gain compression power output of 18 dBm at 18 GHz. This increases to 19 dBm for frequencies below 15 GHz.<>
{"title":"A broadband low noise dual gate FET distributed amplifier","authors":"W. Thompson","doi":"10.1109/MCS.1989.37252","DOIUrl":"https://doi.org/10.1109/MCS.1989.37252","url":null,"abstract":"A 2 to 18 GHz monolithic GaAs low-noise distributed amplifier with 10 dB nominal gain was designed and built using the standard Texas Instrument GaAs foundry process. This process incorporates ground vias, metal-insulator-metal (MIM) capacitors and air bridges. The amplifier uses 0.5- mu m-gate ion-implanted dual-gate FETs (DGFETs). The noise figure is less than 5.7 dB over the 2 to 18 GHz band and less than 4.0 dB from 3 to 13 GHz. The DGFET amplifier provides gain control capability; with 5 V and 60 mA operating bias it provides 10-dB nominal gain, input return loss better than 10 dB, and output return loss better than 8 dB. Lower power consumption was demonstrated at 5 V and 30 mA. With this reduced bias the nominal gain drops to 8 dB and the noise figure degrades by 0.3 dB. Increasing the bias to 7 V and 90 mA increases the nominal gain to 11 dB while degrading the noise figure by 0.3 dB. This increased bias gives the amplifier medium power capability, with a 1-dB gain compression power output of 18 dBm at 18 GHz. This increases to 19 dBm for frequencies below 15 GHz.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133508555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design, fabrication and measured performance are presented for a DC-18 GHz GaAs MESFET monolithic variable-slope gain-equalizer IC. The IC design uses a modified bridged-T configuration using two GaAs MESFETs. This provides an attenuation slope of -0.67 dB/GHz at the maximum linear slope state with a minimum insertion loss of 2.7 dB at 18 GHz and a deviation of linearity less than 0.25 dB from DC to 18 GHz. The slope is electrically variable from -0.67 to +0.22 dB/GHz. The input and output VSWRs are less than 2:1 over the entire frequency and control range.<>
{"title":"A DC-18 GHz GaAs MESFET monolithic variable slope gain-equalizer IC","authors":"H.J. Sun, B. Morley","doi":"10.1109/MCS.1989.37267","DOIUrl":"https://doi.org/10.1109/MCS.1989.37267","url":null,"abstract":"The design, fabrication and measured performance are presented for a DC-18 GHz GaAs MESFET monolithic variable-slope gain-equalizer IC. The IC design uses a modified bridged-T configuration using two GaAs MESFETs. This provides an attenuation slope of -0.67 dB/GHz at the maximum linear slope state with a minimum insertion loss of 2.7 dB at 18 GHz and a deviation of linearity less than 0.25 dB from DC to 18 GHz. The slope is electrically variable from -0.67 to +0.22 dB/GHz. The input and output VSWRs are less than 2:1 over the entire frequency and control range.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114858313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Ayaki, T. Shimura, K. Hosogi, T. Kato, Y. Nakajima, Masayuki Sakai, Y. Kohno, H. Nakano, N. Tanino
The design and fabrication of a 12-GHz-band, 4-stage, monolithic super-low-noise amplifier using self-aligned multilayer gate FETs is described. The device uses a self-aligned multilayer gate FET (SAMFET) with a LDD structure and a buried p-layer. The 0.3- mu m-gate FET used in the amplifier produces a typical noise figure of 1.07 dB with an associated gain of 9.0 dB at 12 GHz. The amplifier gives a minimum noise figure of 1.58 dB with a gain of 29 dB at 12 GHz: the noise figure is less than 1.76 dB with an associated gain as high as 28 dB in the frequency range from 11.7 to 12.7 GHz.<>
{"title":"A 12 GHz-band super low-noise amplifier using a self-aligned gate MESFET","authors":"N. Ayaki, T. Shimura, K. Hosogi, T. Kato, Y. Nakajima, Masayuki Sakai, Y. Kohno, H. Nakano, N. Tanino","doi":"10.1109/MCS.1989.37250","DOIUrl":"https://doi.org/10.1109/MCS.1989.37250","url":null,"abstract":"The design and fabrication of a 12-GHz-band, 4-stage, monolithic super-low-noise amplifier using self-aligned multilayer gate FETs is described. The device uses a self-aligned multilayer gate FET (SAMFET) with a LDD structure and a buried p-layer. The 0.3- mu m-gate FET used in the amplifier produces a typical noise figure of 1.07 dB with an associated gain of 9.0 dB at 12 GHz. The amplifier gives a minimum noise figure of 1.58 dB with a gain of 29 dB at 12 GHz: the noise figure is less than 1.76 dB with an associated gain as high as 28 dB in the frequency range from 11.7 to 12.7 GHz.<<ETX>>","PeriodicalId":377911,"journal":{"name":"Digest of Papers.,Microwave and Millimeter-Wave Monolithic Circuits Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114936585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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