Sehrash Ashraf, Shahnaz Parveen Khattak, Mohammad Tariq Iqbal
Across the globe, COVID-19 had far-reaching impacts that included healthcare facilities, public health, as well as all forms of transport. Hospitals were experiencing staffing shortages at the same time as patients were experiencing healthcare issues. Consequently, even in developing countries without full access to technology, remote health monitoring became necessary. There was a greater severity of the pandemic in countries with fewer financial and technical resources. It became evident that such remote health monitoring systems that not only allowed the user to monitor their basic health information, but also to communicate that information to healthcare personnel, were essential. In this article, we present an open-source, Internet-of-Things (IoT)-based health monitoring system that is intended to mitigate the basic healthcare challenges posed by remote areas of developing countries. To facilitate remote health monitoring, an IoT server has been configured on an ESP32 chip as part of this study. The microcontroller was also connected to a Max 30100 sensor, a DHT11 sensor, and a global positioning system GPS module. As a result of this, the user is able to measure the heart rate (HR), blood oxygen level (SpO2), human body temperature, ambient temperature and humidity, as well as the location of the user. Through the internet protocol, the important vital signs can be displayed in real time on the dashboard using a private communication network. This article presents the details of a complete system design, implementation, testing, and results. Such systems can help limit the spread of infectious diseases like COVID-19.
{"title":"Design and Implementation of an Open-Source and Internet-of-Things-Based Health Monitoring System","authors":"Sehrash Ashraf, Shahnaz Parveen Khattak, Mohammad Tariq Iqbal","doi":"10.3390/jlpea13040057","DOIUrl":"https://doi.org/10.3390/jlpea13040057","url":null,"abstract":"Across the globe, COVID-19 had far-reaching impacts that included healthcare facilities, public health, as well as all forms of transport. Hospitals were experiencing staffing shortages at the same time as patients were experiencing healthcare issues. Consequently, even in developing countries without full access to technology, remote health monitoring became necessary. There was a greater severity of the pandemic in countries with fewer financial and technical resources. It became evident that such remote health monitoring systems that not only allowed the user to monitor their basic health information, but also to communicate that information to healthcare personnel, were essential. In this article, we present an open-source, Internet-of-Things (IoT)-based health monitoring system that is intended to mitigate the basic healthcare challenges posed by remote areas of developing countries. To facilitate remote health monitoring, an IoT server has been configured on an ESP32 chip as part of this study. The microcontroller was also connected to a Max 30100 sensor, a DHT11 sensor, and a global positioning system GPS module. As a result of this, the user is able to measure the heart rate (HR), blood oxygen level (SpO2), human body temperature, ambient temperature and humidity, as well as the location of the user. Through the internet protocol, the important vital signs can be displayed in real time on the dashboard using a private communication network. This article presents the details of a complete system design, implementation, testing, and results. Such systems can help limit the spread of infectious diseases like COVID-19.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135462903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation.
{"title":"A Low-Power Analog Cell for Implementing Spiking Neural Networks in 65 nm CMOS","authors":"John S. Venker, Luke Vincent, Jeff Dix","doi":"10.3390/jlpea13040055","DOIUrl":"https://doi.org/10.3390/jlpea13040055","url":null,"abstract":"A Spiking Neural Network (SNN) is realized within a 65 nm CMOS process to demonstrate the feasibility of its constituent cells. Analog hardware neural networks have shown improved energy efficiency in edge computing for real-time-inference applications, such as speech recognition. The proposed network uses a leaky integrate and fire neuron scheme for computation, interleaved with a Spike Timing Dependent Plasticity (STDP) circuit for implementing synaptic-like weights. The low-power, asynchronous analog neurons and synapses are tailored for the VLSI environment needed to effectively make use of hardware SSN systems. To demonstrate functionality, a feed-forward Spiking Neural Network composed of two layers, the first with ten neurons and the second with six, is implemented. The neuron design operates with 2.1 pJ of power per spike and 20 pJ per synaptic operation.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136032495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Alper Goksoy, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu, Umit Y. Ogras
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.
{"title":"Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip","authors":"A. Alper Goksoy, Sahil Hassan, Anish Krishnakumar, Radu Marculescu, Ali Akoglu, Umit Y. Ogras","doi":"10.3390/jlpea13040056","DOIUrl":"https://doi.org/10.3390/jlpea13040056","url":null,"abstract":"Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136033010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Muhammad Faisal Siddiqui, Mukesh Kumar Maheshwari, Muhammad Raza, Aurangzeb Rashid Masud
This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.
{"title":"Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology","authors":"Muhammad Faisal Siddiqui, Mukesh Kumar Maheshwari, Muhammad Raza, Aurangzeb Rashid Masud","doi":"10.3390/jlpea13040054","DOIUrl":"https://doi.org/10.3390/jlpea13040054","url":null,"abstract":"This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135301711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.
{"title":"A Power-Gated 8-Transistor Physically Unclonable Function Accelerates Evaluation Speeds","authors":"Yujin Zheng, Alex Yakovlev, Alex Bystrov","doi":"10.3390/jlpea13040053","DOIUrl":"https://doi.org/10.3390/jlpea13040053","url":null,"abstract":"The proposed 8-Transistor (8T) Physically Unclonable Function (PUF), in conjunction with the power gating technique, can significantly accelerate a single evaluation cycle more than 100,000 times faster than a 6-Transistor (6T) Static Random-Access Memory (SRAM) PUF. The 8T PUF is built to swiftly eliminate data remanence and maximise physical mismatch. Moreover, a two-phase power gating module is devised to provide controllable power on/off cycles for the chosen PUF clusters in order to facilitate fast statistical measurements and curb the in-rush current. The architecture and hardware implementation of the power-gated PUF are developed to accommodate fast multiple evaluations of PUF Responses. The fast speed enables a new data processing method, which coordinates Dark-bit masking and Multiple Temporal Majority Voting (TMV) in different Process, Voltage and Temperature (PVT) corners or during field usage, hence greatly reducing the Bit Error Rate (BER) and the hardware penalty for error correction. The designs are based on the UMC 65 nm technology and aim to tape out an Application-Specific Integrated Circuit (ASIC) chip. Post-layout Monte Carlo (MC) simulations are performed with Cadence, and the extracted PUF Responses are processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion in PUF Responses, which comprise the novelty of this approach.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135246586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
António Roque, Duarte M. Sousa, Pedro J. Sebastião, Vítor Silva, Elmano Margato
The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is a core aspect for the development of new FFC systems. A new hybrid solution is described that allows controlling the power of semiconductors by switches (ON/OFF mode) or as a linear device. The approach avoids over-design of the power supply and makes it possible to implement new low power solutions constituting a novel design by joining a continuous match between the ON/OFF mode and the linear control of the power semiconductor devices.
{"title":"FFC-NMR Power Supply with Hybrid Control of the Semiconductor Devices","authors":"António Roque, Duarte M. Sousa, Pedro J. Sebastião, Vítor Silva, Elmano Margato","doi":"10.3390/jlpea13030052","DOIUrl":"https://doi.org/10.3390/jlpea13030052","url":null,"abstract":"The performance of FFC-NMR power supplies is evaluated not only considering the technique requirements but also comparing efficiencies and power consumption. Since the characteristics of FFC-NMR power supplies depend on the power circuit topology and on the control solutions, the control design is a core aspect for the development of new FFC systems. A new hybrid solution is described that allows controlling the power of semiconductors by switches (ON/OFF mode) or as a linear device. The approach avoids over-design of the power supply and makes it possible to implement new low power solutions constituting a novel design by joining a continuous match between the ON/OFF mode and the linear control of the power semiconductor devices.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135015715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anna Richelli, Paolo Faustini, Andrea Rosa, Luigi Colalongo
Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.
{"title":"An Investigation of the Operating Principles and Power Consumption of Digital-Based Analog Amplifiers","authors":"Anna Richelli, Paolo Faustini, Andrea Rosa, Luigi Colalongo","doi":"10.3390/jlpea13030051","DOIUrl":"https://doi.org/10.3390/jlpea13030051","url":null,"abstract":"Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136362371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thomas Mountford, Abhijitt Dhavlle, Andrew Tevebaugh, N. Mansoor, Sai Manoj Pudukotai Dinakarrao, A. Ganguly
In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.
{"title":"Address Obfuscation to Protect against Hardware Trojans in Network-on-Chips","authors":"Thomas Mountford, Abhijitt Dhavlle, Andrew Tevebaugh, N. Mansoor, Sai Manoj Pudukotai Dinakarrao, A. Ganguly","doi":"10.3390/jlpea13030050","DOIUrl":"https://doi.org/10.3390/jlpea13030050","url":null,"abstract":"In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43337495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Object detection, a more advanced application of computer vision than image classification, utilizes deep neural networks to predict objects in an input image and determine their locations through bounding boxes. The field of artificial intelligence has increasingly focused on the demands of autonomous driving, which require both high accuracy and fast inference speeds. This research paper aims to address this demand by introducing an efficient lightweight network for object detection specifically designed for self-driving vehicles. The proposed network, named MobDet3, incorporates a modified MobileNetV3 as its backbone, leveraging its lightweight convolutional neural network algorithm to extract and aggregate image features. Furthermore, the network integrates altered techniques in computer vision and adjusts to the most recent iteration of the PyTorch framework. The MobDet3 network enhances not only object positioning ability but also the reusability of feature maps across different scales. Extensive evaluations were conducted to assess the effectiveness of the proposed network, utilizing an autonomous driving dataset, as well as large-scale everyday human and object datasets. These evaluations were performed on NXP BlueBox 2.0, an advanced edge development platform designed for autonomous vehicles. The results demonstrate that the proposed lightweight object detection network achieves a mean precision of up to 58.30% on the BDD100K dataset and a high inference speed of up to 88.92 frames per second on NXP BlueBox 2.0, making it well-suited for real-time object detection in autonomous driving applications.
{"title":"An Improved Lightweight Network Using Attentive Feature Aggregation for Object Detection in Autonomous Driving","authors":"Priyank Kalgaonkar, M. El-Sharkawy","doi":"10.3390/jlpea13030049","DOIUrl":"https://doi.org/10.3390/jlpea13030049","url":null,"abstract":"Object detection, a more advanced application of computer vision than image classification, utilizes deep neural networks to predict objects in an input image and determine their locations through bounding boxes. The field of artificial intelligence has increasingly focused on the demands of autonomous driving, which require both high accuracy and fast inference speeds. This research paper aims to address this demand by introducing an efficient lightweight network for object detection specifically designed for self-driving vehicles. The proposed network, named MobDet3, incorporates a modified MobileNetV3 as its backbone, leveraging its lightweight convolutional neural network algorithm to extract and aggregate image features. Furthermore, the network integrates altered techniques in computer vision and adjusts to the most recent iteration of the PyTorch framework. The MobDet3 network enhances not only object positioning ability but also the reusability of feature maps across different scales. Extensive evaluations were conducted to assess the effectiveness of the proposed network, utilizing an autonomous driving dataset, as well as large-scale everyday human and object datasets. These evaluations were performed on NXP BlueBox 2.0, an advanced edge development platform designed for autonomous vehicles. The results demonstrate that the proposed lightweight object detection network achieves a mean precision of up to 58.30% on the BDD100K dataset and a high inference speed of up to 88.92 frames per second on NXP BlueBox 2.0, making it well-suited for real-time object detection in autonomous driving applications.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47182392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.
{"title":"TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface","authors":"Hideto Kayashima, H. Amano","doi":"10.3390/jlpea13030048","DOIUrl":"https://doi.org/10.3390/jlpea13030048","url":null,"abstract":"The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47923866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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