This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.
{"title":"Ultra-Low Power Programmable Bandwidth Capacitively-Coupled Chopper Instrumentation Amplifier Using 0.2 V Supply for Biomedical Applications","authors":"Xuan Thanh Pham, Xuan Thuc Kieu, Manh Kha Hoang","doi":"10.3390/jlpea13020037","DOIUrl":"https://doi.org/10.3390/jlpea13020037","url":null,"abstract":"This paper presents a capacitively coupled chopper instrumentation amplifier (CCIA) with ultra-low power consumption and programmable bandwidth for biomedical applications. To achieve a flexible bandwidth from 0.2 to 10 kHz without additional power consumption, a programmable Miller compensation technique was proposed and used in the CCIA. By using a Squeezed inverter amplifier (SQI) that employs a 0.2-V supply, the proposed CCIA addresses the primary noise source in the first stage, resulting in high noise power efficiency. The proposed CCIA is designed using a 0.18 µm CMOS technology process and has a chip area of 0.083 mm2. With a power consumption of 0.47 µW at 0.2 and 0.8 V supply, the proposed amplifier architecture achieves a thermal noise of 28 nV/√Hz, an input-related noise (IRN) of 0.9 µVrms, a closed-loop gain (AV) of 40 dB, a power supply rejection ratio (PSRR) of 87.6 dB, and a common-mode rejection ratio (CMRR) of 117.7 dB according to post-simulation data. The proposed CCIA achieves a noise efficiency factor (NEF) of 1.47 and a power efficiency factor (PEF) of 0.56, which allows comparison with the latest research results.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49621516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The dark-silicon challenge poses a design problem for future many-core systems. As a result of this, several techniques have been introduced to improve the number of processing elements that can be powered on. One of the techniques employed by many is Task Migration. In this paper, an Ageing Task Migration Aware for High-Performance Computing (AMA) is proposed to improve the lifetime of nodes. The proposed method determines which clusters applications are mapped to and migrates high-demand tasks amongst nodes to improve the lifetime at every epoch. Experimental results show that the proposed method outperforms state-of-the-art techniques by more than 10%.
{"title":"AMA: An Ageing Task Migration Aware for High-Performance Computing","authors":"Emmanuel Ofori-Attah, Michael Opoku Agyeman","doi":"10.3390/jlpea13020036","DOIUrl":"https://doi.org/10.3390/jlpea13020036","url":null,"abstract":"The dark-silicon challenge poses a design problem for future many-core systems. As a result of this, several techniques have been introduced to improve the number of processing elements that can be powered on. One of the techniques employed by many is Task Migration. In this paper, an Ageing Task Migration Aware for High-Performance Computing (AMA) is proposed to improve the lifetime of nodes. The proposed method determines which clusters applications are mapped to and migrates high-demand tasks amongst nodes to improve the lifetime at every epoch. Experimental results show that the proposed method outperforms state-of-the-art techniques by more than 10%.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45814875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pangsui Usifu Linge, Tony Gerges, P. Bevilacqua, J. Duchamp, P. Benech, J. Verdier, P. Lombard, Michel Cabrera, P. Tsafack, F. Mieyeville, Bruno Allard
This work details the design and experimental characterization of a 2D rectenna for scavenging radio frequency energy at 2.45 GHz (WiFi band), fabricated on polylactic acid polymer (PLA) using a plastronics approach. PLA is the RF substrate of both antenna and rectifier. The two transmission line (TTL) approach is used to characterize the substrate properties to be considered during design. A linearly polarized patch antenna with microstrip transmission feeding is connected to a single series diode rectifier through a T-matching network. The antenna has simulated and measured gain of 7.6 dB and 7.5 dB, respectively. The rectifier has a measured DC output power of 0.96 μW at an optimal load of 2 kΩ under RF input power of −20 dBm at 2.45 GHz. The power conversion efficiency is 9.6% in the latter conditions for a 54 × 36 mm patch antenna of a 1.5 mm thick PLA substrate obtained from additive manufacturing. The power conversion efficiency reaches a value of 28.75% when the input power is −10 dBm at 2.45 GHz. This corresponds to a peak DC power of 28.75 μW when the optimal load is 1.5 kΩ. The results compare significantly with the ones of a similar rectenna circuit manufactured on preferred RF substrate.
{"title":"Evaluation of Polylactic Acid Polymer as a Substrate in Rectenna for Ambient Radiofrequency Energy Harvesting","authors":"Pangsui Usifu Linge, Tony Gerges, P. Bevilacqua, J. Duchamp, P. Benech, J. Verdier, P. Lombard, Michel Cabrera, P. Tsafack, F. Mieyeville, Bruno Allard","doi":"10.3390/jlpea13020034","DOIUrl":"https://doi.org/10.3390/jlpea13020034","url":null,"abstract":"This work details the design and experimental characterization of a 2D rectenna for scavenging radio frequency energy at 2.45 GHz (WiFi band), fabricated on polylactic acid polymer (PLA) using a plastronics approach. PLA is the RF substrate of both antenna and rectifier. The two transmission line (TTL) approach is used to characterize the substrate properties to be considered during design. A linearly polarized patch antenna with microstrip transmission feeding is connected to a single series diode rectifier through a T-matching network. The antenna has simulated and measured gain of 7.6 dB and 7.5 dB, respectively. The rectifier has a measured DC output power of 0.96 μW at an optimal load of 2 kΩ under RF input power of −20 dBm at 2.45 GHz. The power conversion efficiency is 9.6% in the latter conditions for a 54 × 36 mm patch antenna of a 1.5 mm thick PLA substrate obtained from additive manufacturing. The power conversion efficiency reaches a value of 28.75% when the input power is −10 dBm at 2.45 GHz. This corresponds to a peak DC power of 28.75 μW when the optimal load is 1.5 kΩ. The results compare significantly with the ones of a similar rectenna circuit manufactured on preferred RF substrate.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45888310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Riccardo Della Sala, Valerio Spinogatti, Cristian Bocciarelli, F. Centurelli, A. Trifiletti
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.
{"title":"A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR","authors":"Riccardo Della Sala, Valerio Spinogatti, Cristian Bocciarelli, F. Centurelli, A. Trifiletti","doi":"10.3390/jlpea13020035","DOIUrl":"https://doi.org/10.3390/jlpea13020035","url":null,"abstract":"In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44780238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.
{"title":"In-Pipeline Processor Protection against Soft Errors","authors":"Johannes Mach, L. Kohútka, P. Cicák","doi":"10.3390/jlpea13020033","DOIUrl":"https://doi.org/10.3390/jlpea13020033","url":null,"abstract":"The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger area, and higher power consumption. We propose a protection technique that only slightly affects the maximal frequency. The area and power consumption increase are comparable with dual lockstep architectures. A reaction to faults and the ability to recover from them is similar to triple modular redundancy architectures. The novelty lies in applying redundancy into the processor’s pipeline and its separation into two sections. The protection provides fast detection of faults, simple recovery by a flush of the pipeline, and allows a large prediction unit to be unprotected. A proactive component automatically scrubs a register file to prevent fault accumulation. The whole protection scheme can be fully implemented at the register transfer level. We present the protection scheme implemented inside the RISC-V core with the RV32IMC instruction set. Simulations confirm that the protection can handle the injected faults. Synthesis shows that the protection lowers the maximum frequency by only about 3.9%. The area increased by 108% and power consumption by 119%.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43702408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, S. Vlassis
In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.
{"title":"A Time-Mode PWM 1st Order Low-Pass Filter","authors":"Konstantinos P. Pagkalos, Orfeas Panetas-Felouris, S. Vlassis","doi":"10.3390/jlpea13020032","DOIUrl":"https://doi.org/10.3390/jlpea13020032","url":null,"abstract":"In this work, a first-order low-pass filter is proposed as suitable for time-mode PWM signal processing. In time-mode PWM signal processing, the pulse width of a rectangular pulse is the processing variable. The filter is constructed using basic time-mode building blocks such as time registers and time adders and so it is characterized by low complexity which can lead to the modular and versatile design of higher-order filters. All the building blocks of the filter were designed and verified in a TSMC 65 nm technology process. The sampling frequency was 5 MHz, the gain of the filter at low frequencies was at −0.016 dB, the cut-off frequency was 1.2323 MHz, and the power consumption was around 59.1 μW.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43110630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Manuel Boebel, Fabian Frei, F. Blumensaat, C. Ebi, M. Meli, Andreas Rüst
Drinking water is becoming increasingly scarce as the world’s population grows and climate change continues. However, there is great potential to improve drinking water pipelines, as 30% of fresh water is lost between the supplier and consumer. While systematic process monitoring could play a crucial role in the early detection and repair of leaks, current practice requires manual inspection, which is both time-consuming and costly. This project envisages maintenance-free measurements at numerous locations within the underground infrastructure, a goal that is to be achieved through the use of a harvesting device mounted on the water pipe. This device extracts energy from the temperature difference between the water pipe and the soil using a TEG (thermoelectric generator), takes sensor measurements, processes the data and transmits it wirelessly via LoRaWAN. We built 16 harvesting devices, installed them in four locations and continuously evaluated their performance throughout the project. In this paper, we focus on two devices of a particular type. The data for a full year show that enough energy was available on 94% of the days, on average, to take measurements and transmit data. This study demonstrates that it is possible to power highly constrained sensing devices with energy harvesting in underground environments.
{"title":"Batteryless Sensor Devices for Underground Infrastructure—A Long-Term Experiment on Urban Water Pipes","authors":"Manuel Boebel, Fabian Frei, F. Blumensaat, C. Ebi, M. Meli, Andreas Rüst","doi":"10.3390/jlpea13020031","DOIUrl":"https://doi.org/10.3390/jlpea13020031","url":null,"abstract":"Drinking water is becoming increasingly scarce as the world’s population grows and climate change continues. However, there is great potential to improve drinking water pipelines, as 30% of fresh water is lost between the supplier and consumer. While systematic process monitoring could play a crucial role in the early detection and repair of leaks, current practice requires manual inspection, which is both time-consuming and costly. This project envisages maintenance-free measurements at numerous locations within the underground infrastructure, a goal that is to be achieved through the use of a harvesting device mounted on the water pipe. This device extracts energy from the temperature difference between the water pipe and the soil using a TEG (thermoelectric generator), takes sensor measurements, processes the data and transmits it wirelessly via LoRaWAN. We built 16 harvesting devices, installed them in four locations and continuously evaluated their performance throughout the project. In this paper, we focus on two devices of a particular type. The data for a full year show that enough energy was available on 94% of the days, on average, to take measurements and transmit data. This study demonstrates that it is possible to power highly constrained sensing devices with energy harvesting in underground environments.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48737836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biologging refers to the use of animal-borne recording devices to study wildlife behavior. In the case of audio recording, such devices generate large amounts of data over several months, and thus require some level of processing automation for the raw data collected. Academics have widely adopted offline deep-learning-classification algorithms to extract meaningful information from large datasets, mainly using time-frequency signal representations such as spectrograms. Because of the high deployment costs of animal-borne devices, the autonomy/weight ratio remains by far the fundamental concern. Basically, power consumption is addressed using onboard mass storage (no wireless transmission), yet the energy cost associated with data storage activity is far from negligible. In this paper, we evaluate various strategies to reduce the amount of stored data, making the fair assumption that audio will be categorized using a deep-learning classifier at some point of the process. This assumption opens up several scenarios, from straightforward raw audio storage paired with further offline classification on one side, to a fully embedded AI engine on the other side, with embedded audio compression or feature extraction in between. This paper investigates three approaches focusing on data-dimension reduction: (i) traditional inline audio compression, namely ADPCM and MP3, (ii) full deep-learning classification at the edge, and (iii) embedded pre-processing that only computes and stores spectrograms for later offline classification. We characterized each approach in terms of total (sensor + CPU + mass-storage) edge power consumption (i.e., recorder autonomy) and classification accuracy. Our results demonstrate that ADPCM encoding brings 17.6% energy savings compared to the baseline system (i.e., uncompressed raw audio samples). Using such compressed data, a state-of-the-art spectrogram-based classification model still achieves 91.25% accuracy on open speech datasets. Performing inline data-preparation can significantly reduce the amount of stored data allowing for a 19.8% energy saving compared to the baseline system, while still achieving 89% accuracy during classification. These results show that while massive data reduction can be achieved through the use of inline computation of spectrograms, it translates to little benefit on device autonomy when compared to ADPCM encoding, with the added downside of losing original audio information.
生物学是指使用动物传播的记录设备来研究野生动物的行为。在音频记录的情况下，这些设备在几个月内生成大量数据，因此需要对收集的原始数据进行一定程度的自动化处理。学术界广泛采用离线深度学习分类算法从大型数据集中提取有意义的信息，主要使用谱图等时频信号表示。由于动物携带设备的高部署成本，自主性/重量比仍然是迄今为止最基本的问题。基本上，功耗是通过板载大容量存储(没有无线传输)来解决的，但与数据存储活动相关的能源成本远非可以忽略不计。在本文中，我们评估了各种减少存储数据量的策略，并公平地假设音频将在该过程的某个时刻使用深度学习分类器进行分类。这个假设打开了几种场景，从直接的原始音频存储与进一步的离线分类，到完全嵌入的AI引擎，以及嵌入的音频压缩或特征提取。本文研究了三种专注于数据降维的方法:(i)传统的内联音频压缩，即ADPCM和MP3， (ii)边缘的完全深度学习分类，以及(iii)仅计算和存储频谱图以供以后离线分类的嵌入式预处理。我们根据总(传感器+ CPU +大容量存储)边缘功耗(即记录器自主性)和分类准确性来描述每种方法。我们的结果表明，与基线系统(即未压缩的原始音频样本)相比，ADPCM编码节省了17.6%的能源。使用这样的压缩数据，最先进的基于谱图的分类模型在开放语音数据集上仍然达到91.25%的准确率。与基线系统相比，执行内联数据准备可以显著减少存储的数据量，从而节省19.8%的能源，同时在分类过程中仍能达到89%的准确率。这些结果表明，虽然通过使用谱图的内联计算可以实现大量的数据减少，但与ADPCM编码相比，它在设备自主性方面几乎没有什么好处，而且还有丢失原始音频信息的缺点。
{"title":"Energy-Efficient Audio Processing at the Edge for Biologging Applications","authors":"Jonathan Miquel, L. Latorre, S. Chamaillé‐Jammes","doi":"10.3390/jlpea13020030","DOIUrl":"https://doi.org/10.3390/jlpea13020030","url":null,"abstract":"Biologging refers to the use of animal-borne recording devices to study wildlife behavior. In the case of audio recording, such devices generate large amounts of data over several months, and thus require some level of processing automation for the raw data collected. Academics have widely adopted offline deep-learning-classification algorithms to extract meaningful information from large datasets, mainly using time-frequency signal representations such as spectrograms. Because of the high deployment costs of animal-borne devices, the autonomy/weight ratio remains by far the fundamental concern. Basically, power consumption is addressed using onboard mass storage (no wireless transmission), yet the energy cost associated with data storage activity is far from negligible. In this paper, we evaluate various strategies to reduce the amount of stored data, making the fair assumption that audio will be categorized using a deep-learning classifier at some point of the process. This assumption opens up several scenarios, from straightforward raw audio storage paired with further offline classification on one side, to a fully embedded AI engine on the other side, with embedded audio compression or feature extraction in between. This paper investigates three approaches focusing on data-dimension reduction: (i) traditional inline audio compression, namely ADPCM and MP3, (ii) full deep-learning classification at the edge, and (iii) embedded pre-processing that only computes and stores spectrograms for later offline classification. We characterized each approach in terms of total (sensor + CPU + mass-storage) edge power consumption (i.e., recorder autonomy) and classification accuracy. Our results demonstrate that ADPCM encoding brings 17.6% energy savings compared to the baseline system (i.e., uncompressed raw audio samples). Using such compressed data, a state-of-the-art spectrogram-based classification model still achieves 91.25% accuracy on open speech datasets. Performing inline data-preparation can significantly reduce the amount of stored data allowing for a 19.8% energy saving compared to the baseline system, while still achieving 89% accuracy during classification. These results show that while massive data reduction can be achieved through the use of inline computation of spectrograms, it translates to little benefit on device autonomy when compared to ADPCM encoding, with the added downside of losing original audio information.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42605381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a systematic approach to extract electrical equivalent circuit model (ECM) parameters of the Li-ion battery (LIB) based on electrochemical impedance spectroscopy (EIS). Particularly, the proposed approach is suitable to practical applications where the measurement noise can be significant, resulting in a low signal-to-noise ratio. Given the EIS measurements, the proposed approach can be used to obtain the ECM parameters of a battery. Then, a time domain approach is employed to validate the accuracy of estimated ECM parameters. In order to investigate whether the ECM parameters vary as the battery’s state of charge (SOC) changes, the EIS experiment was repeated at nine different SOCs. The experimental results show that the proposed approach is consistent in estimating the ECM parameters. It is found that the battery parameters, such as internal resistance, capacitance and inductance, remain the same for practical SOC ranges starting from 20% until 90%. The ECM parameters saw a significant change at low SOC levels. Furthermore, the experimental data show that the resistive components estimated in the frequency domain are very close to the internal resistance estimated in the time domain. The proposed approach was applied to eight different battery cells consisting of two different manufacturers and produced consistent results.
{"title":"Battery Parameter Analysis through Electrochemical Impedance Spectroscopy at Different State of Charge Levels","authors":"Yuchao Wu, Sneha Sundaresan, B. Balasingam","doi":"10.3390/jlpea13020029","DOIUrl":"https://doi.org/10.3390/jlpea13020029","url":null,"abstract":"This paper presents a systematic approach to extract electrical equivalent circuit model (ECM) parameters of the Li-ion battery (LIB) based on electrochemical impedance spectroscopy (EIS). Particularly, the proposed approach is suitable to practical applications where the measurement noise can be significant, resulting in a low signal-to-noise ratio. Given the EIS measurements, the proposed approach can be used to obtain the ECM parameters of a battery. Then, a time domain approach is employed to validate the accuracy of estimated ECM parameters. In order to investigate whether the ECM parameters vary as the battery’s state of charge (SOC) changes, the EIS experiment was repeated at nine different SOCs. The experimental results show that the proposed approach is consistent in estimating the ECM parameters. It is found that the battery parameters, such as internal resistance, capacitance and inductance, remain the same for practical SOC ranges starting from 20% until 90%. The ECM parameters saw a significant change at low SOC levels. Furthermore, the experimental data show that the resistive components estimated in the frequency domain are very close to the internal resistance estimated in the time domain. The proposed approach was applied to eight different battery cells consisting of two different manufacturers and produced consistent results.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46695246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Ramírez-Angulo, Anindita Paul, Manaswini Gangineni, José Hinojo-Montero, J. Huerta-Chua
The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.
{"title":"Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower","authors":"J. Ramírez-Angulo, Anindita Paul, Manaswini Gangineni, José Hinojo-Montero, J. Huerta-Chua","doi":"10.3390/jlpea13020028","DOIUrl":"https://doi.org/10.3390/jlpea13020028","url":null,"abstract":"The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.","PeriodicalId":38100,"journal":{"name":"Journal of Low Power Electronics and Applications","volume":" ","pages":""},"PeriodicalIF":2.1,"publicationDate":"2023-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49051756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：