Low power, high performance, cost, integration, quality - consumer electronics customers demand all of these, with an increasing sense of urgency and diminishing product cycle times. Properly balancing these factors is the key for success in today's consumer electronics semiconductor industry. SOC designers are faced with challenges of not only delivering complex and highly integrated mixed signal semiconductors, but an equally sophisticated firmware platform. This talk discusses potential solutions in design, methodology and management for this set of seemingly conflicting requirements.
{"title":"We Want It All, and We Want It Now!","authors":"Richard Miller","doi":"10.1109/VLSID.2006.170","DOIUrl":"https://doi.org/10.1109/VLSID.2006.170","url":null,"abstract":"Low power, high performance, cost, integration, quality - consumer electronics customers demand all of these, with an increasing sense of urgency and diminishing product cycle times. Properly balancing these factors is the key for success in today's consumer electronics semiconductor industry. SOC designers are faced with challenges of not only delivering complex and highly integrated mixed signal semiconductors, but an equally sophisticated firmware platform. This talk discusses potential solutions in design, methodology and management for this set of seemingly conflicting requirements.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114401871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics. Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Foundations for statistical parasitic extraction and results from correlation to silicon are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered.
{"title":"Interconnect Process Variations: Theory and Practice","authors":"N. Nagaraj","doi":"10.1109/VLSID.2006.108","DOIUrl":"https://doi.org/10.1109/VLSID.2006.108","url":null,"abstract":"Summary form only for tutorial. Historically, transistor process variations have been studied in great detail. As interconnect becomes a significant portion of circuit performance, signal integrity, power integrity and chip reliability, study of interconnect process variations has gained increased importance. This paper provides a comprehensive overview of types and sources of all aspects interconnect process variations, including via, contact, metal, dielectric barriers and low-k dielectrics. Chemical mechanical polishing (CMP) induced variations and etch induced variations in metal topography are covered. Both systematic and random process variations are discussed. Impact of these interconnect process variations on RC delay, circuit delay, crosstalk noise, voltage drop and EM are discussed. Foundations for statistical parasitic extraction and results from correlation to silicon are discussed. Methods to determine intra-level/inter-level variations and their impact on potential circuit hazards are covered.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127587759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex IP blocks and high-speed buses and interconnection networks. This tutorial addresses the following emerging challenges: architectural exploration, HW/SW co-design, complex control and concurrency, correctness and verification, timing closure, and low-power. The tutorial focuses on language facilities and synthesis techniques that dramatically simplify and shorten the process of correct chip design by raising the level of abstraction on multiple dimensions without sacrificing final hardware quality.
{"title":"Beyond RTL: Advanced Digital System Design","authors":"S. Tasker, R. Nikhil","doi":"10.1109/VLSID.2006.52","DOIUrl":"https://doi.org/10.1109/VLSID.2006.52","url":null,"abstract":"Summary form only for tutorial. This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex IP blocks and high-speed buses and interconnection networks. This tutorial addresses the following emerging challenges: architectural exploration, HW/SW co-design, complex control and concurrency, correctness and verification, timing closure, and low-power. The tutorial focuses on language facilities and synthesis techniques that dramatically simplify and shorten the process of correct chip design by raising the level of abstraction on multiple dimensions without sacrificing final hardware quality.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Kumar, R. Bedi, R. Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. K. Prasad, D. R. Gude
Summary form only for tutorial. SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed.
{"title":"A Comprehensive SoC Design Methodology for Nanometer Design Challenges","authors":"R. Kumar, R. Bedi, R. Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. K. Prasad, D. R. Gude","doi":"10.1109/VLSID.2006.7","DOIUrl":"https://doi.org/10.1109/VLSID.2006.7","url":null,"abstract":"Summary form only for tutorial. SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. This tutorial highlights nanometer chip design challenges and recommends a tool independent design flow which meets the current trends. Covered are ASIC synthesis concepts along with integrated design for testability flow. The focus here is on different approaches to address the convergence challenges during synthesis along with some of the key design optimizations and transformations which would directly impact quality of results (QoR) post P&R. Verification methodology is also discussed. New verification languages and structural tools for linting and code coverage, latest trends in functional verification from the methodology and technology perspective are covered. Also new verification methodology that identifies and provides definition of metrics for functional coverage is reviewed.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130816584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Over the last few years, significant technical advances have increasingly made field programmable gate arrays (FPGAs) the mainstream solution of choice for many digital system designers. This presentation talks about current and future design technologies that enable FPGAs to be used in an ever-increasing range of applications like embedded systems, digital signal processing, and high-speed serial communication, in addition to traditional logic design. It covers the aggressive adoption of process technology in FPGAs, with products in 65 nm technology scheduled for 2006. This talk also presents some of the work done with universities across the globe (and in India) to help further education and research in the area of programmable technologies.
{"title":"Future FPGA Technologies, in Partnership with Universities","authors":"R. Sevcik","doi":"10.1109/VLSID.2006.91","DOIUrl":"https://doi.org/10.1109/VLSID.2006.91","url":null,"abstract":"Summary form only given. Over the last few years, significant technical advances have increasingly made field programmable gate arrays (FPGAs) the mainstream solution of choice for many digital system designers. This presentation talks about current and future design technologies that enable FPGAs to be used in an ever-increasing range of applications like embedded systems, digital signal processing, and high-speed serial communication, in addition to traditional logic design. It covers the aggressive adoption of process technology in FPGAs, with products in 65 nm technology scheduled for 2006. This talk also presents some of the work done with universities across the globe (and in India) to help further education and research in the area of programmable technologies.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132496001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. The design of complex integrated systems faces a growing number of challenges from two frontiers. First, the increasing unpredictability of the progressing semiconductor manufacturing process requires new analysis and optimization approaches that utilize comprehensive modeling of process uncertainties for driving a novel, variation-aware design optimization flow. Second, the increasing system complexity demands new specification methods at higher levels of abstraction that can support efficient architectural exploration, functional verification, and implementation flows. Both challenges require a tight integration of the overall design tool flow resulting in a departure from traditional sequencing of point-tools. In this presentation we discuss a number of these problems in detail and outline possible approaches to their solutions. We further address their impact on algorithmic design and tool integration and discuss new opportunities for academic researchers to help overcome these challenges.
{"title":"Integrated Design Flows - A Battered EDA Slogan or True Challenge for Tool Development and Algorithmic Research","authors":"A. Kuehlmann","doi":"10.1109/VLSID.2006.107","DOIUrl":"https://doi.org/10.1109/VLSID.2006.107","url":null,"abstract":"Summary form only for tutorial. The design of complex integrated systems faces a growing number of challenges from two frontiers. First, the increasing unpredictability of the progressing semiconductor manufacturing process requires new analysis and optimization approaches that utilize comprehensive modeling of process uncertainties for driving a novel, variation-aware design optimization flow. Second, the increasing system complexity demands new specification methods at higher levels of abstraction that can support efficient architectural exploration, functional verification, and implementation flows. Both challenges require a tight integration of the overall design tool flow resulting in a departure from traditional sequencing of point-tools. In this presentation we discuss a number of these problems in detail and outline possible approaches to their solutions. We further address their impact on algorithmic design and tool integration and discuss new opportunities for academic researchers to help overcome these challenges.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114724691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anmol Mathur, M. Fujita, M. Balakrishnan, Raj S. Mitra
Summary form only for tutorial. We define sequential equivalence checking (SEC) to be the process of checking functional equivalence between models that do not satisfy the assumption of one-to-one flop mapping. The need for SEC is being driven by the widespread use of system-level modeling in SystemC/C/C++ for developing golden functional reference models, models for micro-architectural refinement and platforms for software development. This tutorial identifies the design flows where SEC can be effectively used, identify the key technologies needed for developing an effective SEC tool and demonstrate its value proposition in design flows.
{"title":"Sequential Equivalence Checking","authors":"Anmol Mathur, M. Fujita, M. Balakrishnan, Raj S. Mitra","doi":"10.1109/VLSID.2006.145","DOIUrl":"https://doi.org/10.1109/VLSID.2006.145","url":null,"abstract":"Summary form only for tutorial. We define sequential equivalence checking (SEC) to be the process of checking functional equivalence between models that do not satisfy the assumption of one-to-one flop mapping. The need for SEC is being driven by the widespread use of system-level modeling in SystemC/C/C++ for developing golden functional reference models, models for micro-architectural refinement and platforms for software development. This tutorial identifies the design flows where SEC can be effectively used, identify the key technologies needed for developing an effective SEC tool and demonstrate its value proposition in design flows.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123665848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advances in IC and FPGA speeds, pin counts and densities are on a collision course with an electronics company's need to design products in shorter times with optimal performance. Mr. Potts discusses new methodologies and design technology that spans from IC to package to PCB systems and enables concurrent design collaboration among the multiple design disciplines and organizations. He also talks to the need for more automation and functionality in the design of single IC and SiP packages, the ability to assign IC pins to optimize performance at the SiP and systems level, a method of implementing design collaboration between the IC, package and PCB systems' designers, and, revolutionary PCB design technology that could be applied to the design of ICs and their packages.
{"title":"IC/FPGA-Package-PCB Design Collaboration","authors":"H. Potts","doi":"10.1109/VLSID.2006.101","DOIUrl":"https://doi.org/10.1109/VLSID.2006.101","url":null,"abstract":"Advances in IC and FPGA speeds, pin counts and densities are on a collision course with an electronics company's need to design products in shorter times with optimal performance. Mr. Potts discusses new methodologies and design technology that spans from IC to package to PCB systems and enables concurrent design collaboration among the multiple design disciplines and organizations. He also talks to the need for more automation and functionality in the design of single IC and SiP packages, the ability to assign IC pins to optimize performance at the SiP and systems level, a method of implementing design collaboration between the IC, package and PCB systems' designers, and, revolutionary PCB design technology that could be applied to the design of ICs and their packages.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127316952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. System-on-a-chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single chip (SoC) offers the most optimal solution in terms of die size, unit cost, form factor, power, performance and reliability. The SoC development process however implies longer cycle time and high NRE costs. This makes SoCs economically viable only for high volume, high NR applications. The increasing complexity of the systems coupled with the technology scaling challenges have significant negative impact on both the cycle time and the NRE costs. The SoC design challenge in business terms is then to improve execution efficiency at a rate faster than the complexity increase, so as to increase the TAM serviced by SoCs. This talk covers the system and technology trends, highlight their implications and discuss directions to address the ever increasing SoC design challenge.
{"title":"SoC - The Road Ahead","authors":"M. Mehendale","doi":"10.1109/VLSID.2006.149","DOIUrl":"https://doi.org/10.1109/VLSID.2006.149","url":null,"abstract":"Summary form only for tutorial. System-on-a-chip is an evolving definition where a current generation system implemented with multiple chips on a board translates to a system-on-a-chip for the next generation. This is enabled by advances in the semiconductor technology which support increasing levels of single chip integration. For system components which can be efficiently implemented in CMOS, integrating them on a single chip (SoC) offers the most optimal solution in terms of die size, unit cost, form factor, power, performance and reliability. The SoC development process however implies longer cycle time and high NRE costs. This makes SoCs economically viable only for high volume, high NR applications. The increasing complexity of the systems coupled with the technology scaling challenges have significant negative impact on both the cycle time and the NRE costs. The SoC design challenge in business terms is then to improve execution efficiency at a rate faster than the complexity increase, so as to increase the TAM serviced by SoCs. This talk covers the system and technology trends, highlight their implications and discuss directions to address the ever increasing SoC design challenge.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132792388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only for tutorial. The goal of the UNUM project is to show that it is possible to synthesize many different PowerPC models (both existing and new variants) quickly by using a library of microarchitectural IP blocks. The IP blocks and modules that we are developing include instruction decoder, branch predictor, speculative execution structures, ALUs, LI and L2 cache structures, and cache-coherence engines. This project in addition to providing PowerPC gateware for others to use, will shed light on how IP blocks should be written to be easily modifiable and reusable.
{"title":"UNUM: A Tinker-Toy Approach to Building Multicore PowerPC Microarchitectures","authors":"Arvind","doi":"10.1109/VLSID.2006.164","DOIUrl":"https://doi.org/10.1109/VLSID.2006.164","url":null,"abstract":"Summary form only for tutorial. The goal of the UNUM project is to show that it is possible to synthesize many different PowerPC models (both existing and new variants) quickly by using a library of microarchitectural IP blocks. The IP blocks and modules that we are developing include instruction decoder, branch predictor, speculative execution structures, ALUs, LI and L2 cache structures, and cache-coherence engines. This project in addition to providing PowerPC gateware for others to use, will shed light on how IP blocks should be written to be easily modifiable and reusable.","PeriodicalId":382435,"journal":{"name":"VLSI design (Print)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116355875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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