Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In this paper, we extend previous work and propose an alternative analytical model to compute System-level Vulnerability Factor (SVF) for both write-through and write-back data caches. In our proposed analytical model, we take into account both read frequency and error masking to compute system-level vulnerability of data cache. Previously suggested modeling techniques overlook the issues of read frequency and error masking, mainly focusing on time periods in which an error could propagate in the system. In this work we show that overlooking these two parameters can significantly impact the system-level VFs for data caches. We report our estimations for SPEC’2K benchmarks and compare to previously suggested models. Our experimental results show that the proposed modeling technique changes previous VF estimations by up to 40%.
{"title":"System-Level Vulnerability Estimation for Data Caches","authors":"Alireza Haghdoost, H. Asadi, A. Baniasadi","doi":"10.1109/PRDC.2010.9","DOIUrl":"https://doi.org/10.1109/PRDC.2010.9","url":null,"abstract":"Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In this paper, we extend previous work and propose an alternative analytical model to compute System-level Vulnerability Factor (SVF) for both write-through and write-back data caches. In our proposed analytical model, we take into account both read frequency and error masking to compute system-level vulnerability of data cache. Previously suggested modeling techniques overlook the issues of read frequency and error masking, mainly focusing on time periods in which an error could propagate in the system. In this work we show that overlooking these two parameters can significantly impact the system-level VFs for data caches. We report our estimations for SPEC’2K benchmarks and compare to previously suggested models. Our experimental results show that the proposed modeling technique changes previous VF estimations by up to 40%.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121875462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hanawa, Hitoshi Koizumi, Takayuki Banzai, M. Sato, Shin'ichi Miura, Tadatoshi Ishii, Hidehisa Takamizawa
D-Cloud is a software testing environment for dependable parallel and distributed systems using cloud computing technology. We use Eucalyptus as cloud management software to manage virtual machines designed based on QEMU, called FaultVM, which have a fault injection mechanism. D-Cloud enables the test procedures to be automated using a large amount of computing resources in the cloud by interpreting the system configuration and the test scenario written in XML in D-Cloud front end and enables tests including hardware faults by emulating hardware faults by FaultVM flexibly. In the present paper, we describe the customization facility of FaultVM used to add new device models. We use SpecC, which is a system description language, to describe the behavior of devices, and a simulator generated from the description by SpecC is linked and integrated into FaultVM. This also makes the definition and injection of faults flexible without the modification of the original QEMU source codes. This facility allows D-Cloud to be used to test distributed systems with customized devices.
{"title":"Customizing Virtual Machine with Fault Injector by Integrating with SpecC Device Model for a Software Testing Environment D-Cloud","authors":"T. Hanawa, Hitoshi Koizumi, Takayuki Banzai, M. Sato, Shin'ichi Miura, Tadatoshi Ishii, Hidehisa Takamizawa","doi":"10.1109/PRDC.2010.37","DOIUrl":"https://doi.org/10.1109/PRDC.2010.37","url":null,"abstract":"D-Cloud is a software testing environment for dependable parallel and distributed systems using cloud computing technology. We use Eucalyptus as cloud management software to manage virtual machines designed based on QEMU, called FaultVM, which have a fault injection mechanism. D-Cloud enables the test procedures to be automated using a large amount of computing resources in the cloud by interpreting the system configuration and the test scenario written in XML in D-Cloud front end and enables tests including hardware faults by emulating hardware faults by FaultVM flexibly. In the present paper, we describe the customization facility of FaultVM used to add new device models. We use SpecC, which is a system description language, to describe the behavior of devices, and a simulator generated from the description by SpecC is linked and integrated into FaultVM. This also makes the definition and injection of faults flexible without the modification of the original QEMU source codes. This facility allows D-Cloud to be used to test distributed systems with customized devices.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128867855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Andrés J. Gonzalez, B. Helvik, Jon Kåre Hellan, P. Kuusela
Dependencies between failures in operational networks may have a huge impact on their reliability and availability. In this paper we analyze failure logs to identify simultaneous and potentially correlated failures in routers and links of an IP backbone network. We show that the actual behavior of failure processes does not support the independence assumption commonly used in theoretical studies. Scatter plots are presented to visualize the failure processes, and it is seen that geographical adjacency has a pronounced effect. The existence of high correlation coefficients and high autocorrelation in some failure processes was observed. A formal analysis confirms this. The consequences of these dependencies on the provisioning of guaranteed availability are briefly discussed.
{"title":"Analysis of Dependencies between Failures in the UNINETT IP Backbone Network","authors":"Andrés J. Gonzalez, B. Helvik, Jon Kåre Hellan, P. Kuusela","doi":"10.1109/PRDC.2010.12","DOIUrl":"https://doi.org/10.1109/PRDC.2010.12","url":null,"abstract":"Dependencies between failures in operational networks may have a huge impact on their reliability and availability. In this paper we analyze failure logs to identify simultaneous and potentially correlated failures in routers and links of an IP backbone network. We show that the actual behavior of failure processes does not support the independence assumption commonly used in theoretical studies. Scatter plots are presented to visualize the failure processes, and it is seen that geographical adjacency has a pronounced effect. The existence of high correlation coefficients and high autocorrelation in some failure processes was observed. A formal analysis confirms this. The consequences of these dependencies on the provisioning of guaranteed availability are briefly discussed.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121199745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The occurrence of deadlocks should be controlled effectively by their detection and resolution, but may sometimes lead to a serious system failure. This fact implies that deadlock detection scheduling should be designed from the view points of not only the performance trade-off between overall message usage and deadlock persistence time but also the prevention of the system failure. In this paper, we reformulate the Ling {it{et al.}}'s deadlock detection scheduling problem (2006) in the presence of system failures, and derive the optimal deadlock detection time minimizing the long-run average cost per unit time. By introducing the message complexities of the deadlock detection and resolution algorithms being used, we investigate the asymptotically optimal frequency of deadlock detection scheduling in terms of the number of distributed processes through the well-known Landau notation.
{"title":"Deadlock Detection Scheduling for Distributed Processes in the Presence of System Failures","authors":"A. Izumi, T. Dohi, N. Kaio","doi":"10.1109/PRDC.2010.49","DOIUrl":"https://doi.org/10.1109/PRDC.2010.49","url":null,"abstract":"The occurrence of deadlocks should be controlled effectively by their detection and resolution, but may sometimes lead to a serious system failure. This fact implies that deadlock detection scheduling should be designed from the view points of not only the performance trade-off between overall message usage and deadlock persistence time but also the prevention of the system failure. In this paper, we reformulate the Ling {it{et al.}}'s deadlock detection scheduling problem (2006) in the presence of system failures, and derive the optimal deadlock detection time minimizing the long-run average cost per unit time. By introducing the message complexities of the deadlock detection and resolution algorithms being used, we investigate the asymptotically optimal frequency of deadlock detection scheduling in terms of the number of distributed processes through the well-known Landau notation.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122768362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper refines statistical inference of computer virus propagation with maximum likelihood (ML) estimation. In particular, in order to utilize actual infection data that are opened in Web sites, we reformulate classical stochastic models by Markovian arrival processes (MAPs). The reformulated models lead to plausible parameter estimation based on the ML estimation. We propose efficient algorithms to compute the ML estimates of epidemic models using the EM (expectation-maximization) algorithm. Experiments illustrate the estimation of virus propagation with real infection data by our methods. Finally we refer to characterization of virus propagation from the view point of stochastic modeling.
{"title":"Estimating Computer Virus Propagation Based on Markovian Arrival Processes","authors":"H. Okamura, T. Dohi","doi":"10.1109/PRDC.2010.36","DOIUrl":"https://doi.org/10.1109/PRDC.2010.36","url":null,"abstract":"This paper refines statistical inference of computer virus propagation with maximum likelihood (ML) estimation. In particular, in order to utilize actual infection data that are opened in Web sites, we reformulate classical stochastic models by Markovian arrival processes (MAPs). The reformulated models lead to plausible parameter estimation based on the ML estimation. We propose efficient algorithms to compute the ML estimates of epidemic models using the EM (expectation-maximization) algorithm. Experiments illustrate the estimation of virus propagation with real infection data by our methods. Finally we refer to characterization of virus propagation from the view point of stochastic modeling.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115734996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The most important character of real-time systems is that they have stringent timing deadlines that must be guaranteed. A hard real-time system is required to complete its operations before all its timing deadlines. For a given task set, it is useful in an engineering context to know what changes to period can be made to a task that will deliver a schedulable system. In this paper, we develop the sensitivity analysis of task period for EDF scheduled systems on a uniprocessor. We prove that a minimum task period can be determined by a single pass of the QPA algorithm, an improved scheme is presented by using different initial values of the period. The approaches developed for sensitivity analysis of task period are therefore as efficient as QPA, and are easily incorporated into a system design support tool.
{"title":"Sensitivity Analysis of the Minimum Task Period for Arbitrary Deadline Real-Time Systems","authors":"Fengxiang Zhang, A. Burns, Sanjoy Baruah","doi":"10.1109/PRDC.2010.16","DOIUrl":"https://doi.org/10.1109/PRDC.2010.16","url":null,"abstract":"The most important character of real-time systems is that they have stringent timing deadlines that must be guaranteed. A hard real-time system is required to complete its operations before all its timing deadlines. For a given task set, it is useful in an engineering context to know what changes to period can be made to a task that will deliver a schedulable system. In this paper, we develop the sensitivity analysis of task period for EDF scheduled systems on a uniprocessor. We prove that a minimum task period can be determined by a single pass of the QPA algorithm, an improved scheme is presented by using different initial values of the period. The approaches developed for sensitivity analysis of task period are therefore as efficient as QPA, and are easily incorporated into a system design support tool.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123647717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a speculative Byzantine algorithm base on Zyzzyva which has high performance for applying to peer to peer (P2P). We adopt a hybrid P2P system with monitor node to improve the performance of pure P2P system.
{"title":"A Speculative Byzantine Algorithm for P2P System","authors":"Y. Matsumoto, Hiromi Kobayashi","doi":"10.1109/PRDC.2010.17","DOIUrl":"https://doi.org/10.1109/PRDC.2010.17","url":null,"abstract":"This paper presents a speculative Byzantine algorithm base on Zyzzyva which has high performance for applying to peer to peer (P2P). We adopt a hybrid P2P system with monitor node to improve the performance of pure P2P system.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"13 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123628556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Patooghy, Mansour Shafaei, S. Miremadi, Hajar Falahati, Somayyeh Taheri
This paper proposes an efficient cross talk mitigation method for Network-on-Chips (NoCs). The proposed method investigates flits in each packet to minimize the number of harmful transition patterns appearing on the communication channels of NoC. To do this, the content of every flit is rotated with respect to the previously flit sent through the channel. Rotation is done to find a rotated version of the flit which minimizes the number of harmful transition patterns. A tag field is added into the rotated flit to enable the receiving side to recover the original flit. Maximum number of rotations is bounded by a fixed value to minimize the timing and power overheads of the proposed method. Evaluation of the proposed method is done in both analytical and simulation manners. VHDL-based simulations are carried out for several channel widths and several tag widths. Simulation results confirm that the proposed method effectively overcomes the cross talk problem while its timing and power overheads are negligible. Results of analytical evaluation are also in agreement with the simulation results.
{"title":"FiRot: An Efficient Crosstalk Mitigation Method for Network-on-Chips","authors":"A. Patooghy, Mansour Shafaei, S. Miremadi, Hajar Falahati, Somayyeh Taheri","doi":"10.1109/PRDC.2010.29","DOIUrl":"https://doi.org/10.1109/PRDC.2010.29","url":null,"abstract":"This paper proposes an efficient cross talk mitigation method for Network-on-Chips (NoCs). The proposed method investigates flits in each packet to minimize the number of harmful transition patterns appearing on the communication channels of NoC. To do this, the content of every flit is rotated with respect to the previously flit sent through the channel. Rotation is done to find a rotated version of the flit which minimizes the number of harmful transition patterns. A tag field is added into the rotated flit to enable the receiving side to recover the original flit. Maximum number of rotations is bounded by a fixed value to minimize the timing and power overheads of the proposed method. Evaluation of the proposed method is done in both analytical and simulation manners. VHDL-based simulations are carried out for several channel widths and several tag widths. Simulation results confirm that the proposed method effectively overcomes the cross talk problem while its timing and power overheads are negligible. Results of analytical evaluation are also in agreement with the simulation results.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126558130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jed Kao-Tung Chang, Shaoshan Liu, J. Gaudiot, Chen Liu
Security is very important in modern life due to most information is now stored in digital format. A good security mechanism will keep information secrecy and integrity, hence, plays an important role in modern information exchange. However, cryptography algorithms are extremely expensive in terms of execution time. To make data not easily being cracked, many arithmetic and logical operations will be executed in the encryption/decryption process with many data movement. This means the cryptographic applications are both computation and memory intensive. Using a general-purpose processor for this scenario would not be very cost-effective. This study addresses this problem. Compared to the previous designs, we used a performance analyzer to identify “hotspot” functions across a set of benchmarks. The hotspot function consumes a substantial amount of the execution time of the specific algorithm. Then we translate these hotspot functions into hardware accelerators to improve the performance. Overall we achieve 34 – 83 folds of speedup.
{"title":"The Performance Analysis and Hardware Acceleration of Crypto-computations for Enhanced Security","authors":"Jed Kao-Tung Chang, Shaoshan Liu, J. Gaudiot, Chen Liu","doi":"10.1109/PRDC.2010.21","DOIUrl":"https://doi.org/10.1109/PRDC.2010.21","url":null,"abstract":"Security is very important in modern life due to most information is now stored in digital format. A good security mechanism will keep information secrecy and integrity, hence, plays an important role in modern information exchange. However, cryptography algorithms are extremely expensive in terms of execution time. To make data not easily being cracked, many arithmetic and logical operations will be executed in the encryption/decryption process with many data movement. This means the cryptographic applications are both computation and memory intensive. Using a general-purpose processor for this scenario would not be very cost-effective. This study addresses this problem. Compared to the previous designs, we used a performance analyzer to identify “hotspot” functions across a set of benchmarks. The hotspot function consumes a substantial amount of the execution time of the specific algorithm. Then we translate these hotspot functions into hardware accelerators to improve the performance. Overall we achieve 34 – 83 folds of speedup.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"74 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The manual development of system reliability models such as fault trees could be costly and error prone in practice. In this paper, we focus on the problems of some traditional dynamic fault trees and present our static solutions to represent dynamic relations such as functional and sequential dependencies. The implementation of a tool for the automatic synthesis of our static fault trees from SysML system models is introduced.
{"title":"Automatic Static Fault Tree Analysis from System Models","authors":"Jianwen Xiang, Kazuo Yanoo","doi":"10.1109/PRDC.2010.35","DOIUrl":"https://doi.org/10.1109/PRDC.2010.35","url":null,"abstract":"The manual development of system reliability models such as fault trees could be costly and error prone in practice. In this paper, we focus on the problems of some traditional dynamic fault trees and present our static solutions to represent dynamic relations such as functional and sequential dependencies. The implementation of a tool for the automatic synthesis of our static fault trees from SysML system models is introduced.","PeriodicalId":382974,"journal":{"name":"2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127906604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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