Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009196
Yukai Chen, E. Macii, M. Poncino
Despite the wide body of literature on the sizing of energy storage devices available in the domain of electrical energy systems, the problem has not drawn much attention in the area of battery-powered electronic systems.
{"title":"Workload-driven frequency-aware battery sizing","authors":"Yukai Chen, E. Macii, M. Poncino","doi":"10.1109/ISLPED.2017.8009196","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009196","url":null,"abstract":"Despite the wide body of literature on the sizing of energy storage devices available in the domain of electrical energy systems, the problem has not drawn much attention in the area of battery-powered electronic systems.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133256791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009200
Farhana Parveen, Shaahin Angizi, Zhezhi He, Deliang Fan
In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in traditional logic-in-memory designs. The computed logic output could be simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in conventional Von-Neumann computing systems. We further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed design can achieve 70.15% and 80.87% lower energy consumption compared to CMOS-ASIC and CMOL-AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation, but with 60.65% less area overhead.
{"title":"Low power in-memory computing based on dual-mode SOT-MRAM","authors":"Farhana Parveen, Shaahin Angizi, Zhezhi He, Deliang Fan","doi":"10.1109/ISLPED.2017.8009200","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009200","url":null,"abstract":"In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in traditional logic-in-memory designs. The computed logic output could be simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in conventional Von-Neumann computing systems. We further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed design can achieve 70.15% and 80.87% lower energy consumption compared to CMOS-ASIC and CMOL-AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation, but with 60.65% less area overhead.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114962601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009166
Donkyu Baek, Caiwen Ding, Sheng Lin, Donghwa Shin, Jaemin Kim, X. Lin, Yanzhi Wang, N. Chang
Conventional internal combustion engine vehicles (ICEV) generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The heat energy maintains the engine temperature for efficient combustion as a good aspect, but the amount of heat generation is excessive and eventually breaks the engine components unless advanced cooling system technologies are supported such as high-capacity radiators, elaborated water jackets, high-flow rate coolant pumps, etc. The excessive heat dissipation plays a key role on a poor fuel economy, but reclamation of the heat energy has not been a main focus of vehicle design. This work is first to propose a cross-layer, system-level solution to enhance thermoelectric generator (TEG) array efficiency introducing online reconfiguration of TEG modules. The proposed method is useful to any sort of TEG array to reclaim wasted heat energy because cooling and exhaust systems generally have different inlet and outlet temperatures. In this paper, we deploy the proposed method to vehicle radiator heat energy harvesting, which does not affect the vehicle performance while exhaust heat energy harvesting may disturb the combustion and emission control integrity. We introduce a novel TEG reconfiguration and maximize the TEG array output in spite of dynamic change of the coolant flow rate and temperature, which results in a huge variation in the coolant temperature distribution of inside the radiator. The proposed method enables all the TEG modules to run at or close to their maximum power points (MPP) under dynamically changing vehicle operating conditions. Experimental results show up to a 34% enhancement compared with a fixed array structure, which is a common practice.
{"title":"Reconfigurable thermoelectric generators for vehicle radiators energy harvesting","authors":"Donkyu Baek, Caiwen Ding, Sheng Lin, Donghwa Shin, Jaemin Kim, X. Lin, Yanzhi Wang, N. Chang","doi":"10.1109/ISLPED.2017.8009166","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009166","url":null,"abstract":"Conventional internal combustion engine vehicles (ICEV) generally have less than a 30% of fuel efficiency, and the most wasted energy is dissipated in the form of heat energy. The heat energy maintains the engine temperature for efficient combustion as a good aspect, but the amount of heat generation is excessive and eventually breaks the engine components unless advanced cooling system technologies are supported such as high-capacity radiators, elaborated water jackets, high-flow rate coolant pumps, etc. The excessive heat dissipation plays a key role on a poor fuel economy, but reclamation of the heat energy has not been a main focus of vehicle design. This work is first to propose a cross-layer, system-level solution to enhance thermoelectric generator (TEG) array efficiency introducing online reconfiguration of TEG modules. The proposed method is useful to any sort of TEG array to reclaim wasted heat energy because cooling and exhaust systems generally have different inlet and outlet temperatures. In this paper, we deploy the proposed method to vehicle radiator heat energy harvesting, which does not affect the vehicle performance while exhaust heat energy harvesting may disturb the combustion and emission control integrity. We introduce a novel TEG reconfiguration and maximize the TEG array output in spite of dynamic change of the coolant flow rate and temperature, which results in a huge variation in the coolant temperature distribution of inside the radiator. The proposed method enables all the TEG modules to run at or close to their maximum power points (MPP) under dynamically changing vehicle operating conditions. Experimental results show up to a 34% enhancement compared with a fixed array structure, which is a common practice.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116633612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009208
Brandon Reagen, José Miguel Hernández-Lobato, Robert Adolf, M. Gelbart, P. Whatmough, Gu-Yeon Wei, D. Brooks
In this paper we propose using machine learning to improve the design of deep neural network hardware accelerators. We show how to adapt multi-objective Bayesian optimization to overcome a challenging design problem: optimizing deep neural network hardware accelerators for both accuracy and energy efficiency. DNN accelerators exhibit all aspects of a challenging optimization space: the landscape is rough, evaluating designs is expensive, the objectives compete with each other, and both design spaces (algorithmic and microarchitectural) are unwieldy. With multi-objective Bayesian optimization, the design space exploration is made tractable and the design points found vastly outperform traditional methods across all metrics of interest.
{"title":"A case for efficient accelerator design space exploration via Bayesian optimization","authors":"Brandon Reagen, José Miguel Hernández-Lobato, Robert Adolf, M. Gelbart, P. Whatmough, Gu-Yeon Wei, D. Brooks","doi":"10.1109/ISLPED.2017.8009208","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009208","url":null,"abstract":"In this paper we propose using machine learning to improve the design of deep neural network hardware accelerators. We show how to adapt multi-objective Bayesian optimization to overcome a challenging design problem: optimizing deep neural network hardware accelerators for both accuracy and energy efficiency. DNN accelerators exhibit all aspects of a challenging optimization space: the landscape is rough, evaluating designs is expensive, the objectives compete with each other, and both design spaces (algorithmic and microarchitectural) are unwieldy. With multi-objective Bayesian optimization, the design space exploration is made tractable and the design points found vastly outperform traditional methods across all metrics of interest.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127560553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009188
Augusto J. Vega, A. Buyuktosunoglu, P. Bose
This paper presents a visionary proposal for a distributed (or decentralized) power/thermal control mechanism that applies the bio-inspired artificial intelligence paradigm of swarm intelligence. The target use case is a future many-core processor. The paper reports a high-level concept-phase specification of the proposed solution approach in a research setting. The emphasis is on highlighting the key challenges and pitfalls that must be dealt with in transitioning this research into full product deployment.
{"title":"Invited paper: Secure swarm intelligence: A new approach to many-core power management","authors":"Augusto J. Vega, A. Buyuktosunoglu, P. Bose","doi":"10.1109/ISLPED.2017.8009188","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009188","url":null,"abstract":"This paper presents a visionary proposal for a distributed (or decentralized) power/thermal control mechanism that applies the bio-inspired artificial intelligence paradigm of swarm intelligence. The target use case is a future many-core processor. The paper reports a high-level concept-phase specification of the proposed solution approach in a research setting. The emphasis is on highlighting the key challenges and pitfalls that must be dealt with in transitioning this research into full product deployment.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125518410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009159
Jihwan Park, Gi-Moon Hong, Mino Kim, Joo-Hyung Chae, Suhwan Kim
In this paper, we propose a low power transceiver (TRx) suitable for a wired intra-body area network (BAN) communication. The proposed transceiver is designed with relaxation oscillator which is appropriate for this low frequency (< 50MHz) application. To lessen the complexity of building this BAN system, we use clock edge modulation (CEM) data as sending or receiving data, and this allows the transceiver to operate without reference clock. The relaxation oscillator in this transceiver is designed to be able to generate CEM data pattern as well as a clock, so this can minimize power consumption in designing additional block related to transmission. Proposed circuit operates up to 36MHz with 1.0V supply voltage. It consumes 1.26uW at an input data rate of 10Mbps and achieves 0.13pJ/bit of energy per bit even though the circuit is implemented in a 0.18µm CMOS technology.
在本文中，我们提出了一种适合于有线体内局域网(BAN)通信的低功耗收发器(TRx)。所提出的收发器设计有松弛振荡器，适用于这种低频(< 50MHz)应用。为了减少构建BAN系统的复杂性，我们使用时钟边缘调制(CEM)数据作为发送或接收数据，这允许收发器在没有参考时钟的情况下工作。该收发器中的弛豫振荡器被设计为能够生成CEM数据模式和时钟，因此在设计与传输相关的附加块时可以将功耗降至最低。该电路在1.0V电源电压下工作至36MHz。在输入数据速率为10Mbps时，功耗为1.26uW，即使电路采用0.18 μ m CMOS技术实现，每比特的能量也为0.13pJ/bit。
{"title":"A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication","authors":"Jihwan Park, Gi-Moon Hong, Mino Kim, Joo-Hyung Chae, Suhwan Kim","doi":"10.1109/ISLPED.2017.8009159","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009159","url":null,"abstract":"In this paper, we propose a low power transceiver (TRx) suitable for a wired intra-body area network (BAN) communication. The proposed transceiver is designed with relaxation oscillator which is appropriate for this low frequency (< 50MHz) application. To lessen the complexity of building this BAN system, we use clock edge modulation (CEM) data as sending or receiving data, and this allows the transceiver to operate without reference clock. The relaxation oscillator in this transceiver is designed to be able to generate CEM data pattern as well as a clock, so this can minimize power consumption in designing additional block related to transmission. Proposed circuit operates up to 36MHz with 1.0V supply voltage. It consumes 1.26uW at an input data rate of 10Mbps and achieves 0.13pJ/bit of energy per bit even though the circuit is implemented in a 0.18µm CMOS technology.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116149732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009170
S. Samal, S. Khandelwal, A. Khan, S. Salahuddin, C. Hu, S. Lim
We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.
{"title":"Full chip power benefits with negative capacitance FETs","authors":"S. Samal, S. Khandelwal, A. Khan, S. Salahuddin, C. Hu, S. Lim","doi":"10.1109/ISLPED.2017.8009170","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009170","url":null,"abstract":"We study, for the first time, full chip power benefits of negative capacitance FET (NCFET) device technology for commercial-grade GDSII-level designs. Owing to sub-60mV/decade characteristics, NCFETs provide significantly higher drive-current than standard FETs at a given voltage, enabling significant iso-performance power savings by lowering VDD. We use SPICE models of NCFETs corresponding to 14nm node, which incorporate experimentally calibrated models of ferroelectric. We then characterize NCFET-based standard-cell libraries followed by full-chip NCFET-based GDSII-level design implementations of different benchmarks. Our results show that even with increased device capacitance, we can achieve about 4× (up to 74.7%) full-chip power reduction with low-VDD NCFETs over nominal VDD baseline FETs at iso-performance. The power savings are consistent across multiple benchmarks and are higher for low power designs.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133602486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009179
B. Gunna, Lakshmi Bhamidipati, H. Homayoun, Avesta Sasan
This paper, formulates a novel technique that explores on-chip IR drop reduction and instantaneous demanded peak-current reduction simultaneously. Proposed solution leverages unused timing slacks, and schedules the clock arrival times to relax the peak current which is delivered through each via-stack in the on-chip IR hot-spots. In addition, this paper formulates and introduces a new evaluation metric which aids us in assessing the improvement in the voltage-noise gaurdband after application of the proposed mitigation technique. The strength of the proposed IR mitigation technique is that, in addition to timing information, it considers the power delivery network and cell placement information while scheduling the clock arrival times to achieve the best results. Application of the proposed solution to a selected IWLS benchmarks reduces the peak dynamic IR-drop by ∼49%, and the peak demanded current by ∼44%.
{"title":"Spatial and temporal scheduling of clock arrival times for IR hot-spot mitigation, reformulation of peak current reduction","authors":"B. Gunna, Lakshmi Bhamidipati, H. Homayoun, Avesta Sasan","doi":"10.1109/ISLPED.2017.8009179","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009179","url":null,"abstract":"This paper, formulates a novel technique that explores on-chip IR drop reduction and instantaneous demanded peak-current reduction simultaneously. Proposed solution leverages unused timing slacks, and schedules the clock arrival times to relax the peak current which is delivered through each via-stack in the on-chip IR hot-spots. In addition, this paper formulates and introduces a new evaluation metric which aids us in assessing the improvement in the voltage-noise gaurdband after application of the proposed mitigation technique. The strength of the proposed IR mitigation technique is that, in addition to timing information, it considers the power delivery network and cell placement information while scheduling the clock arrival times to achieve the best results. Application of the proposed solution to a selected IWLS benchmarks reduces the peak dynamic IR-drop by ∼49%, and the peak demanded current by ∼44%.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117172758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009185
S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, R. Krishnamurthy
Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99 min-entropy with 3pJ/bit energy-efficiency.
{"title":"Invited paper: Ultra-low energy security circuit primitives for IoT platforms","authors":"S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, R. Krishnamurthy","doi":"10.1109/ISLPED.2017.8009185","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009185","url":null,"abstract":"Low-area energy-efficient security primitives are key building blocks for enabling end-to-end content protection, user authentication in IoT platforms. This paper describes 3 designs that employ energy-efficient circuit techniques with optimal hardware-friendly arithmetic for seamless integration into area/battery constrained IoT systems: 1) A 2040-gate AES accelerator achieving 289Gbps/W efficiency in 22nm CMOS, 2) Hardened hybrid Physically Unclonable Function (PUF) circuit to generate a 100% stable encryption key. 3) All-digital TRNG to achieve >0.99 min-entropy with 3pJ/bit energy-efficiency.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009209
Li Li, J. Wang, Xiaorui Wang, Handong Ye, Ziang Hu
Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.
{"title":"SceneMan: Bridging mobile apps with system energy manager via scenario notification","authors":"Li Li, J. Wang, Xiaorui Wang, Handong Ye, Ziang Hu","doi":"10.1109/ISLPED.2017.8009209","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009209","url":null,"abstract":"Power management on current mobile devices relies on OS modules known as DVFS governors. However, existing governors determine system configuration only based on low-level information such as CPU load without any input about application-level behaviors. In particular, there exists no communication from mobile apps to energy managers. We find that information about app usage scenarios (e.g., gaming, video chatting) can usually help energy manager perform a better job and achieve more energy savings. Although app-level energy optimizations have been proposed, they generally focus on single usage scenarios and do not address optimization across multiple scenarios. In this paper, we propose SceneMan, an energy optimization framework for mobile apps based on usage scenario notification. SceneMan has three components: an API, a scenario notifier, and an energy manager. The key idea is to make energy managers aware of app-level scenarios. At runtime, apps notify the energy manager about their usage scenarios with provided APIs used by developers. The energy manager then takes appropriate actions to minimize energy consumption of the running scenario while meeting performance requirements. Energy optimization across scenarios can thus be easily achieved. The framework requires little extra programming effort and can help apps achieve better energy efficiency in a transparent way. We implement our system on a Nexus 6 smartphone and test it with 13 real-world apps under 2 usage scenarios, namely, gaming and video chatting. We achieve up to 33.2% energy savings with a worst-case performance loss of 5.1%.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125015560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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