Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009162
Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li, Huazhong Yang
Convolutional Neural Network (CNN) has become one of the most successful technologies for visual classification and other applications. As CNN models continue to evolve and adopt different kernel sizes in various applications, it is necessary for the hardware architecture to support reconfigurability. Previous FPGAs and programmable ASICs are fine-grained reconfigurable but with energy efficiency compromise. Considering specific features of CNNs, this paper presents an energy efficient coarse-grained reconfigurable architecture, denoted as CORAL. An application-specific configuration neural block is proposed for convolution operations with reconfigurable data quantization to reduce both energy consumption and on-chip memory requirements. An optimal data loading strategy is presented for CORAL to achieve the best energy efficiency. Experimental results show that CORAL improves 80.0% energy efficiency while reduces 78.9% chip area and 81.0% reconfiguration time compared with the best up-to-date programmable ASIC solution.
{"title":"CORAL: Coarse-grained reconfigurable architecture for Convolutional Neural Networks","authors":"Zhe Yuan, Yongpan Liu, Jinshan Yue, Jinyang Li, Huazhong Yang","doi":"10.1109/ISLPED.2017.8009162","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009162","url":null,"abstract":"Convolutional Neural Network (CNN) has become one of the most successful technologies for visual classification and other applications. As CNN models continue to evolve and adopt different kernel sizes in various applications, it is necessary for the hardware architecture to support reconfigurability. Previous FPGAs and programmable ASICs are fine-grained reconfigurable but with energy efficiency compromise. Considering specific features of CNNs, this paper presents an energy efficient coarse-grained reconfigurable architecture, denoted as CORAL. An application-specific configuration neural block is proposed for convolution operations with reconfigurable data quantization to reduce both energy consumption and on-chip memory requirements. An optimal data loading strategy is presented for CORAL to achieve the best energy efficiency. Experimental results show that CORAL improves 80.0% energy efficiency while reduces 78.9% chip area and 81.0% reconfiguration time compared with the best up-to-date programmable ASIC solution.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129853760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009175
Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, S. Lim
In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.
{"title":"Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition","authors":"Kyungwook Chang, Deepak Kadetotad, Yu Cao, Jae-sun Seo, S. Lim","doi":"10.1109/ISLPED.2017.8009175","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009175","url":null,"abstract":"In recent years, deep learning has become widespread for various real-world recognition tasks. In addition to recognition accuracy, energy efficiency is another grand challenge to enable local intelligence in edge devices. In this paper, we investigate the adoption of monolithic 3D IC (M3D) technology for deep learning hardware design, using speech recognition as a test vehicle. M3D has recently proven to be one of the leading contenders to address the power, performance and area (PPA) scaling challenges in advanced technology nodes. Our study encompasses the influence of key parameters in DNN hardware implementations towards energy efficiency, including DNN architectural choices, underlying workloads, and tier partitioning choices in M3D. Our post-layout M3D designs, together with hardware-efficient sparse algorithms, produce power savings beyond what can be achieved using conventional 2D ICs. Experimental results show that M3D offers 22.3% iso-performance power saving, convincingly demonstrating its entitlement as a solution for DNN ASICs. We further present architectural guidelines for M3D DNNs to maximize the power saving.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121648969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009160
William Y. Li, Hyung Seok Kim, K. Chandrashekar, K. M. Nguyen, A. Ravi
In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture imposes significant challenges to support different data rate simultaneously. In high bandwidth I/O, LC oscillators are preferred for low jitter, but the limited frequency range confines the data rate tuning. Multiple LC-PLLs are costly in area and power, and sometimes infeasible due to heavily congested I/O area. Worse still, couplings between inductors could lead to PLL pulling closing the sampling eye. In this paper, a reconfigurable 0.65–10GHz digital fractional-n clock generator using a single LC PLL, calibrated 0.75/1.25/1.75 digital fractional post dividers for serial I/O is presented. The architecture enables I/O driven by the same PLL to operate at different data rate, thereby reducing power. In addition, multiple LC-PLLs are replaced by one saving area, power, and coupling between LC oscillators. The PLL incorporates a staggered varactor, wide-tuning VCO, and a hysteretic redundant frequency acquisition for improved temperature stability. The prototype in a 32nm high-k metal gate process has a measured TX/RX jitter of 0.9/0.3 ps/σ and dissipates 36.2mW from 1.05V supply.
{"title":"A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O","authors":"William Y. Li, Hyung Seok Kim, K. Chandrashekar, K. M. Nguyen, A. Ravi","doi":"10.1109/ISLPED.2017.8009160","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009160","url":null,"abstract":"In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture imposes significant challenges to support different data rate simultaneously. In high bandwidth I/O, LC oscillators are preferred for low jitter, but the limited frequency range confines the data rate tuning. Multiple LC-PLLs are costly in area and power, and sometimes infeasible due to heavily congested I/O area. Worse still, couplings between inductors could lead to PLL pulling closing the sampling eye. In this paper, a reconfigurable 0.65–10GHz digital fractional-n clock generator using a single LC PLL, calibrated 0.75/1.25/1.75 digital fractional post dividers for serial I/O is presented. The architecture enables I/O driven by the same PLL to operate at different data rate, thereby reducing power. In addition, multiple LC-PLLs are replaced by one saving area, power, and coupling between LC oscillators. The PLL incorporates a staggered varactor, wide-tuning VCO, and a hysteretic redundant frequency acquisition for improved temperature stability. The prototype in a 32nm high-k metal gate process has a measured TX/RX jitter of 0.9/0.3 ps/σ and dissipates 36.2mW from 1.05V supply.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121561117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009197
Yu Liu, Yingyezhe Jin, Peng Li
As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its FPGA implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed FPGA-based neural processor system is up to 29% more energy efficient than a baseline LSM processor with little extra hardware overhead.
{"title":"Exploring sparsity of firing activities and clock gating for energy-efficient recurrent spiking neural processors","authors":"Yu Liu, Yingyezhe Jin, Peng Li","doi":"10.1109/ISLPED.2017.8009197","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009197","url":null,"abstract":"As a model of recurrent spiking neural networks, the Liquid State Machine (LSM) offers a powerful brain-inspired computing platform for pattern recognition and machine learning applications. While operated by processing neural spiking activities, the LSM naturally lends itself to an efficient hardware implementation via exploration of typical sparse firing patterns emerged from the recurrent neural network and smart processing of computational tasks that are orchestrated by different firing events at runtime. We explore these opportunities by presenting a LSM processor architecture with integrated on-chip learning and its FPGA implementation. Our LSM processor leverage the sparsity of firing activities to allow for efficient event-driven processing and activity-dependent clock gating. Using the spoken English letters adopted from the TI46 [1] speech recognition corpus as a benchmark, we show that the proposed FPGA-based neural processor system is up to 29% more energy efficient than a baseline LSM processor with little extra hardware overhead.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134218173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009161
J. Zaini, F. Hameau, T. Taris, D. Morche, P. Audebert, E. Mercier
This paper presents the design of an Ultra Low Power (ULP) inductorless Low Noise Amplifier (LNA) based on a Common Gate (CG) architecture using the back gate control of the Fully-Depleted Silicon-On-Insulator (FDSOI) technology. It demonstrates the potential of the back biasing to lower the power consumption of more than 30 % compared to a design without back biasing, while keeping similar performance. This paper also shows the possibility with the back gate control of this technology to reach additional performance, suitable for the design of tunable LNAs. The proposed LNA has been implemented in ST-Microelectronic 28 nm FDSOI Technology and its active area is only 0.0015 mm2. The measured performance exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF) and an Input referred third-order Intercept Point (IIP3) of −16 dBm. The total power consumption is 300 µW from a 0.6 V supply. The same LNA reached other performance modes at constant Figure of Merit (FoM).
{"title":"A tunable Ultra Low Power inductorless Low Noise Amplifier exploiting body biasing of 28 nm FDSOI technology","authors":"J. Zaini, F. Hameau, T. Taris, D. Morche, P. Audebert, E. Mercier","doi":"10.1109/ISLPED.2017.8009161","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009161","url":null,"abstract":"This paper presents the design of an Ultra Low Power (ULP) inductorless Low Noise Amplifier (LNA) based on a Common Gate (CG) architecture using the back gate control of the Fully-Depleted Silicon-On-Insulator (FDSOI) technology. It demonstrates the potential of the back biasing to lower the power consumption of more than 30 % compared to a design without back biasing, while keeping similar performance. This paper also shows the possibility with the back gate control of this technology to reach additional performance, suitable for the design of tunable LNAs. The proposed LNA has been implemented in ST-Microelectronic 28 nm FDSOI Technology and its active area is only 0.0015 mm2. The measured performance exhibit more than 16 dB of voltage Gain (Gv), 7.3 dB of Noise Figure (NF) and an Input referred third-order Intercept Point (IIP3) of −16 dBm. The total power consumption is 300 µW from a 0.6 V supply. The same LNA reached other performance modes at constant Figure of Merit (FoM).","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126931346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009183
Rathijit Sen, A. Halverson
Dynamically controlling processor frequency to save power while meeting customer Service-Level Objectives (SLOs) can reduce the cost of goods sold for cloud service providers. However, resource governance for Online Transaction Processing (OLTP) workloads in the cloud is complicated by throughput constraints, latency constraints, shallow sleep states that lower processor utilization, and (often) isolation of applications from hardware resource governors. This paper demonstrates a novel frequency governor that improves upon existing Intel P-state and Cpufreq governors in saving power for a cloud OLTP benchmark on Microsoft SQL Server for Linux.
动态控制处理器频率以节省电力，同时满足客户服务水平目标(slo)，可以降低云服务提供商销售商品的成本。然而，云中联机事务处理(OLTP)工作负载的资源治理由于吞吐量约束、延迟约束、降低处理器利用率的浅睡眠状态以及(通常)应用程序与硬件资源调控器的隔离而变得复杂。本文演示了一种新的频率调控器，它改进了现有的Intel P-state和Cpufreq调控器，为Microsoft SQL Server for Linux上的云OLTP基准测试节省了电力。
{"title":"Frequency governors for cloud database OLTP workloads","authors":"Rathijit Sen, A. Halverson","doi":"10.1109/ISLPED.2017.8009183","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009183","url":null,"abstract":"Dynamically controlling processor frequency to save power while meeting customer Service-Level Objectives (SLOs) can reduce the cost of goods sold for cloud service providers. However, resource governance for Online Transaction Processing (OLTP) workloads in the cloud is complicated by throughput constraints, latency constraints, shallow sleep states that lower processor utilization, and (often) isolation of applications from hardware resource governors. This paper demonstrates a novel frequency governor that improves upon existing Intel P-state and Cpufreq governors in saving power for a cloud OLTP benchmark on Microsoft SQL Server for Linux.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116993277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009191
P. K. Chundi, Yini Zhou, Martha A. Kim, E. Kursun, Mingoo Seok
This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.
{"title":"Hotspot monitoring and Temperature Estimation with miniature on-chip temperature sensors","authors":"P. K. Chundi, Yini Zhou, Martha A. Kim, E. Kursun, Mingoo Seok","doi":"10.1109/ISLPED.2017.8009191","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009191","url":null,"abstract":"This paper presents analysis and evaluation of the impact of size and voltage scalability of on-chip temperature sensor on the accuracy of hotspot monitoring and temperature estimation in dynamic thermal management of high performance microprocessors. The analysis is based on both the layout level and the system level across state-of-the-art sensors in terms of accuracy, voltage-scalability, and silicon footprint. Our analysis shows that a sensor having compact footprint and good voltage scalability can be placed on exact hotspot locations, typically among digital cells, significantly improving accuracy in tracking hotspots and estimating temperature of microarchitecture blocks, as compared to two other sensors that have higher sensor-circuit accuracy, large footprint and little voltage scalability limiting flexible placement.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128363420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009153
Tsai-Kan Chien, L. Chiou, Yi-Sung Tsou, S. Sheu, Pei-Hua Wang, M. Tsai, Chih-I Wu
Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.
{"title":"Write-energy-saving ReRAM-based nonvolatile SRAM with redundant bit-write-aware controller for last-level caches","authors":"Tsai-Kan Chien, L. Chiou, Yi-Sung Tsou, S. Sheu, Pei-Hua Wang, M. Tsai, Chih-I Wu","doi":"10.1109/ISLPED.2017.8009153","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009153","url":null,"abstract":"Nonvolatile static random-access memory (NV-SRAM) is a crucial component type for normally-off computing systems. This work proposes a novel 10T2R resistive random-access memory (ReRAM)-based NV-SRAM controller that is aware of redundant bit writes and considers the conditions of redundant bit writes. When data stored in SRAM cells are the same as the data in ReRAM devices, backup can be skipped. Otherwise, backup is performed. As a result, redundant bit-write conditions indicate that energy can be saved when backing up data. Simulations show that as much as 93% of typical energy requirements can be saved when the high resistive state is larger than 10 MΩ. As long as the probability of redundant bit writes is larger than 25%, backup energy saving can be achieved. The ReRAM chip is manufactured with 90 nm CMOS technology and the ReRAM process of the Industrial Technology Research Institute. This design can be applied to L2 and L3 caches.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009174
Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, L. Kim
Applying highly accurate neural networks to mobile devices encounters energy problems in battery-limited mobile environments. To resolve these problems, neuromorphic hardware solutions that enable event-driven operation have been proposed. In this work, we present a novel sparse neuromorphic system that implements an E-I Net algorithm to further improve energy efficiency. We introduce a neuron clock-gating technique that significantly reduces energy consumption by predicting future neuron spike activity without any loss of accuracy. We also propose synaptic pruning to save additional energy with minimal impact on classification accuracy. For fast adaptation to a changing environment, a learning algorithm is implemented in the proposed system. Compared to prior studies, our experimental results illustrate that the proposed system achieves 5.3×–11.4× energy efficiency improvement with comparable accuracy.
{"title":"SENIN: An energy-efficient sparse neuromorphic system with on-chip learning","authors":"Myung-Hoon Choi, Seungkyu Choi, Jaehyeong Sim, L. Kim","doi":"10.1109/ISLPED.2017.8009174","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009174","url":null,"abstract":"Applying highly accurate neural networks to mobile devices encounters energy problems in battery-limited mobile environments. To resolve these problems, neuromorphic hardware solutions that enable event-driven operation have been proposed. In this work, we present a novel sparse neuromorphic system that implements an E-I Net algorithm to further improve energy efficiency. We introduce a neuron clock-gating technique that significantly reduces energy consumption by predicting future neuron spike activity without any loss of accuracy. We also propose synaptic pruning to save additional energy with minimal impact on classification accuracy. For fast adaptation to a changing environment, a learning algorithm is implemented in the proposed system. Compared to prior studies, our experimental results illustrate that the proposed system achieves 5.3×–11.4× energy efficiency improvement with comparable accuracy.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132250514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-01DOI: 10.1109/ISLPED.2017.8009195
James R. B. Bantock, V. Tenentes, B. Al-Hashimi, G. Merrett
Modern mobile devices contain powerful Multi-Processor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.
{"title":"Online tuning of Dynamic Power Management for efficient execution of interactive workloads","authors":"James R. B. Bantock, V. Tenentes, B. Al-Hashimi, G. Merrett","doi":"10.1109/ISLPED.2017.8009195","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009195","url":null,"abstract":"Modern mobile devices contain powerful Multi-Processor System-on-Chips (MPSoCs) that are performance throttled by Dynamic Power Management (DPM) runtime systems to extend battery lifetime. Applications on mobile devices commonly generate highly interactive workloads, dependent on interaction between the processor cores, peripherals, external resources and the user, such as touch input during web-browsing. Inevitably, a subset of interactive workloads are affected by delays caused by data unavailability, e.g. loss or delay of data packets during voice-over-IP. At the same time, the system is required to respond quickly upon data retrieval to ensure that the user Quality of Experience (QoE) metrics (frame-rate, latency, etc.) are not degraded. Traditionally, operating systems have mitigated this problem with periodic sampling or event-driven approaches. Through experimentation using a mobile MPSoC platform, however, we demonstrate that improving the tuning of DPM parameters for certain interactive user inputs can provide energy savings of up to 21% or QoE improvements of up to 36%, when compared with the traditional approach. To capture these improvements, we propose a dynamic modeling of user input and data resource access times (e.g. mobile network bandwidth and latency) for interactive workloads, which is based on workload profiling and which we refer to herein as inelasticity analysis. The proposed approach is implemented through online tuning of a DPM runtime in the Android operating system and is validated through a Monte Carlo simulation of interactive workloads. In comparison to the default DPM tuning, the proposed approach achieves energy savings of 13% or QoE improvement of 27% or a selectable trade-off, e.g. 9% energy savings and 15% QoE improvement.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116953845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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