Pub Date : 1900-01-01DOI: 10.26634/jcir.10.1.18663
Lloyde George Marcus, Innocent-George Nora
First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.
先进先出核心(fifo)是数字系统中用于通过系统缓冲数据以供后期处理的内存存储元件。本文介绍了一种通用FIFO核心的设计和实现，该核心允许根据每个数据字的大小来调整容量。提供状态指示器来指示FIFO是空的、半满的还是满的。存储在FIFO中的数据字数也由系统指定的输出端口表示。还可以使用状态标志来指示大小何时达到预定的阈值。提供了一个单独的接口，允许访问任何地址的数据进行读取。也可以将一个数据字写入FIFO的后面，同时从前面读取另一个数据字。FSM-D架构模型应用于FIFO核心的设计，并使用Xilinx ISE 14.7在VHDL中实现。利用赛灵思ISE平台的ISim逻辑模拟器对实现的核心进行了仿真，结果表明，系统核心的性能符合测试用例的要求。
{"title":"Development of a general purpose First-In-First-Out (FIFO) core","authors":"Lloyde George Marcus, Innocent-George Nora","doi":"10.26634/jcir.10.1.18663","DOIUrl":"https://doi.org/10.26634/jcir.10.1.18663","url":null,"abstract":"First-In-First-Out cores (FIFOs) are memory storage elements that are used in digital systems for buffering data through a system for later processing. This paper presents the design and implementation of a General Purpose FIFO Core which allows adjustment of the capacity along with the size of each data word. Status indicators were provided to indicate whether or not the FIFO was empty, half-full, or full. The number of data words stored in the FIFO was also indicated by designated output ports of the system. A status flag was also available to indicate when the size reached a predetermined threshold value. A separate interface was provided that allowed the data at any address to be accessed for reading. It was also possible to write a data word to the back of the FIFO while another data word was read from the front simultaneously. The FSM-D architectural model was applied to the design of the FIFO Core and the implementation was done in VHDL using the Xilinx ISE 14.7. The implemented core was simulated using ISim Logic Simulator of the Xilinx ISE platform, and it was found that the system core behaved as specified by the test cases.","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"OPTIMAL ALLOCATION AND SIZING OF PV DISTRIBUTED\u0000 GENERATIONS UNDER SEVERAL LOADING CONDITIONS","authors":"A. A. Mahmoud, Ezzat Mohamed, M. Ibrahim","doi":"10.26634/JCIR.7.1.15250","DOIUrl":"https://doi.org/10.26634/JCIR.7.1.15250","url":null,"abstract":"","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129888367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.26634/jcir.10.2.18902
S. Akash, Dey Sayantan, S. Iti
The Analog-to-Digital Converter (ADC), with its wide variety of applications in the electronics and communication domains, is the most crucial unit in every digital gadget. This paper discusses a smart way of converting an input analog signal to its digital counterpart using an innovative Adaptive-Delta modulator, followed by a signal reconstruction process to retrieve the original message. It has done the design in Matrix Laboratory (MATLAB) Simulink, and the hardware implementation is tested on the Xilinx Spartan-6 LX45 FPGA core. This design aims for high-accuracy conversion and optimization of hardware resources. The 1-bit adaptive model is superior in comparison to the traditional delta modulation (DM) scheme while tracking stiff analog input signals, producing a much lower mean square error. The implementation is quite simple as it uses the transmission of 1-bit digital data at a time. On the receiver side, digital-toanalog conversion (DAC) makes use of the same adaptive logic in reconstructing the original input signal. The designed prototype demonstrates its resistance to a wide range of input amplitude and frequency variations. The ADC-DAC design method in this paper is accurate, makes the best use of resources, and is easy to use.
{"title":"An innovative FPGA-based ADC/DAC design using 1-bit adaptive-delta modulation","authors":"S. Akash, Dey Sayantan, S. Iti","doi":"10.26634/jcir.10.2.18902","DOIUrl":"https://doi.org/10.26634/jcir.10.2.18902","url":null,"abstract":"The Analog-to-Digital Converter (ADC), with its wide variety of applications in the electronics and communication domains, is the most crucial unit in every digital gadget. This paper discusses a smart way of converting an input analog signal to its digital counterpart using an innovative Adaptive-Delta modulator, followed by a signal reconstruction process to retrieve the original message. It has done the design in Matrix Laboratory (MATLAB) Simulink, and the hardware implementation is tested on the Xilinx Spartan-6 LX45 FPGA core. This design aims for high-accuracy conversion and optimization of hardware resources. The 1-bit adaptive model is superior in comparison to the traditional delta modulation (DM) scheme while tracking stiff analog input signals, producing a much lower mean square error. The implementation is quite simple as it uses the transmission of 1-bit digital data at a time. On the receiver side, digital-toanalog conversion (DAC) makes use of the same adaptive logic in reconstructing the original input signal. The designed prototype demonstrates its resistance to a wide range of input amplitude and frequency variations. The ADC-DAC design method in this paper is accurate, makes the best use of resources, and is easy to use.","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114200025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SIMULATION OF MATRIX CONVERTER BASED HIGH FREQUENCY\u0000 POWER ELECTRONIC TRACTION TRANSFORMER","authors":"SK Ruksana","doi":"10.26634/jcir.7.2.16683","DOIUrl":"https://doi.org/10.26634/jcir.7.2.16683","url":null,"abstract":"","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IMPLEMENTATION OF POWER REDUCTION IN CMOS CIRCUITS","authors":"D. S. Kumar, K. Rajasekhar","doi":"10.26634/JCIR.7.4.16832","DOIUrl":"https://doi.org/10.26634/JCIR.7.4.16832","url":null,"abstract":"","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SIMULATION OF CASCADED GATE-BASED TERNARY CONTENTADDRESSABLE\u0000MEMORY","authors":"S. Pavithra, P. Deepa","doi":"10.26634/jcir.8.2.18087","DOIUrl":"https://doi.org/10.26634/jcir.8.2.18087","url":null,"abstract":"","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"86 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122179771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.26634/jcir.10.2.18978
Varun, Krishan Bal, Tripathi Rohit
In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.
{"title":"Leakage power optimization using sleeping approaches in TSPC D flip-flop","authors":"Varun, Krishan Bal, Tripathi Rohit","doi":"10.26634/jcir.10.2.18978","DOIUrl":"https://doi.org/10.26634/jcir.10.2.18978","url":null,"abstract":"In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116088535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.26634/jcir.10.1.18845
Sahu Nidhi, Sahu Sandeep
Power electronic devices play a vital role in manufacturing process, research and development because it delivers high efficiency, low cost, rapid operation, and optimal size. In recent years, power electronic devices have become widely employed in a variety of fields. Harmonics have a substantial impact on power systems and the main sources of harmonics are nonlinear loads and energy conversion devices such as static converters, choppers, cyclo-converters, battery charging systems, and heating elements, among others. To reduce harmonics, different filtration technologies are available, with the shunt active power filter being one of the most significant and effective. The performance of a shunt active power filter based on synchronous reference frame theory is explored and the efficiency is improved utilising the satin bower bird optimization approach.
{"title":"Performance analysis of shunt active filter based on srf theory using metaheuristic optimization technique for nonlinear loads","authors":"Sahu Nidhi, Sahu Sandeep","doi":"10.26634/jcir.10.1.18845","DOIUrl":"https://doi.org/10.26634/jcir.10.1.18845","url":null,"abstract":"Power electronic devices play a vital role in manufacturing process, research and development because it delivers high efficiency, low cost, rapid operation, and optimal size. In recent years, power electronic devices have become widely employed in a variety of fields. Harmonics have a substantial impact on power systems and the main sources of harmonics are nonlinear loads and energy conversion devices such as static converters, choppers, cyclo-converters, battery charging systems, and heating elements, among others. To reduce harmonics, different filtration technologies are available, with the shunt active power filter being one of the most significant and effective. The performance of a shunt active power filter based on synchronous reference frame theory is explored and the efficiency is improved utilising the satin bower bird optimization approach.","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SIMULATION OF HIGH FREQUENCY STEP DOWN OF SINGLE\u0000 PHASE MATRIX CONVERTER AS AN UNIVERSAL CONVERTER","authors":"D. K. V., R. S. K.","doi":"10.26634/jcir.7.1.15726","DOIUrl":"https://doi.org/10.26634/jcir.7.1.15726","url":null,"abstract":"","PeriodicalId":408741,"journal":{"name":"i-manager's Journal on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115573202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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