Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222363
Minsu Choi, N. Park, F. Lombardi, Yong-Bin Kim, V. Piuri
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies the largest portion of the SoC area; this trend much likely will continue in the future as it is widely anticipated that it will approach the 94% level by the year 2014. As memory cells are more prone to defects and faults than logic cells, redundancy has been extensively used for enhancing defect and fault tolerance through repair by spare (row and column) replacement. Unlike legacy PCB (printed circuit board) or MCM (multichip module) based systems, embedded cores cannot be physically replaced once they are fabricated onto a SoC. To realize both enhanced manufacturing yield and field reliability, ATE (automated test equipment) and BISR (built-in-self-repair) are utilized to allocate redundancy for the embedded memory cores. As ATEs (for the repair of manufacturing defects) and BISR (for repairing field faults) rely on the provided redundancy (rows and columns), spare partition and utilization techniques are proposed in this paper to achieve an optimal combination of yield and reliability for embedded memory cores. Parametric simulation results for the single dimensional (i. e., spare columns) and two-dimensional (i. e., both spare columns and rows) cases are provided.
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Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222354
B. Prince
DRAMs have historically been high volume, standard, commodity memories. Today with many high volume applications having differing requirements, DRAMs are becoming more application specific. This talk discusses a variety of application specific DRAMs including those with high speed interfaces such as the DDR and DDRII SDRAM and those with speed enhancing internal architectures; DRAMs with low power internal design techniques for use in battery operated systems; DRAMs with graphics enhancements such as high speed point-to-point interfaces and various internal graphics functions; DRAMs for networking such as ternary CAMs, SRAM look-alike DRAMs with pseudo-static operation for both high performance networking and battery operated asynchronous and synchronous applications; and low voltage power supply DRAMs.
{"title":"Application specific DRAMs Today","authors":"B. Prince","doi":"10.1109/MTDT.2003.1222354","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222354","url":null,"abstract":"DRAMs have historically been high volume, standard, commodity memories. Today with many high volume applications having differing requirements, DRAMs are becoming more application specific. This talk discusses a variety of application specific DRAMs including those with high speed interfaces such as the DDR and DDRII SDRAM and those with speed enhancing internal architectures; DRAMs with low power internal design techniques for use in battery operated systems; DRAMs with graphics enhancements such as high speed point-to-point interfaces and various internal graphics functions; DRAMs for networking such as ternary CAMs, SRAM look-alike DRAMs with pseudo-static operation for both high performance networking and battery operated asynchronous and synchronous applications; and low voltage power supply DRAMs.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133645592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-28DOI: 10.1109/MTDT.2003.1222364
R. Aitken
Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defect-based testing for memory concentrates on defect analysis of key parts of the layout and the development of application-independent patterns that will test for likely failures. Testing hundreds of embedded memories on today's SoC designs requires a combination of these approaches in order to assure high quality. Historically, DBT has been enabled in large vertically structured companies that included design, test development, and manufacturing. Many of today's SoCs are built with a different approach, the "customer-owned tooling" (COT) model, where a fables design customer builds a chip with third party IP, including memories, manufactures it through a foundry, and tests it at a separate test house. This complex supply chain cannot be ignored when developing a test solution.
{"title":"Applying defect-based test to embedded memories in a COT model","authors":"R. Aitken","doi":"10.1109/MTDT.2003.1222364","DOIUrl":"https://doi.org/10.1109/MTDT.2003.1222364","url":null,"abstract":"Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defect-based testing for memory concentrates on defect analysis of key parts of the layout and the development of application-independent patterns that will test for likely failures. Testing hundreds of embedded memories on today's SoC designs requires a combination of these approaches in order to assure high quality. Historically, DBT has been enabled in large vertically structured companies that included design, test development, and manufacturing. Many of today's SoCs are built with a different approach, the \"customer-owned tooling\" (COT) model, where a fables design customer builds a chip with third party IP, including memories, manufactures it through a foundry, and tests it at a separate test house. This complex supply chain cannot be ignored when developing a test solution.","PeriodicalId":412381,"journal":{"name":"Records of the 2003 International Workshop on Memory Technology, Design and Testing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132388988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/MTDT.2003.1222353
The following topics are dealt with: application specific DRAMs; cost optimum embedded DRAM design; memory test generation for DRAM defects; linked faults analysis in RAMs; reducing test time of embedded SRAMs; testability-driven optimizer and wrapper generator for embedded memories; ITRS commodity roadmap; electrical simulation model for the Chalcogenide phase-change memory cell.
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