This paper deals with the deployment of industrial control applications on distributed execution supports. These applications are developed according to the IEC 61499 standard. They are based on compositions of event triggered components. The execution support is a network of computational units scheduling OS tasks. The deployment problem consists then in associating components executions to OS tasks. We resolve this problem by proposing a method based on a heuristic and a schedulability analysis. This method has to take into account the execution support limitation while satisfying functional and temporal constraints on application components.
{"title":"A heuristic based method for automatic deployment of distributed component based applications","authors":"M. Khalgui, X. Rebeuf","doi":"10.1109/IES.2006.357471","DOIUrl":"https://doi.org/10.1109/IES.2006.357471","url":null,"abstract":"This paper deals with the deployment of industrial control applications on distributed execution supports. These applications are developed according to the IEC 61499 standard. They are based on compositions of event triggered components. The execution support is a network of computational units scheduling OS tasks. The deployment problem consists then in associating components executions to OS tasks. We resolve this problem by proposing a method based on a heuristic and a schedulability analysis. This method has to take into account the execution support limitation while satisfying functional and temporal constraints on application components.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Real-time embedded architectures consist of software and hardware parts. Meeting non-functional constraints (e.g., real-time constraints) greatly depends on the mappings from the system functionalities to software and hardware components. Thus, there is a strong demand for precise architecture and allocation modeling, amenable to performance analysis. The paper proposes a model-driven approach for the assessment of the quality of allocations of the system functionalities to the architecture. We consider two technical domains: the UML domain for the definition of the model elements, and a non functional property analysis domain, external to UML, used for formal verification. This paper focuses on 1) the specification of expected behavior by UML activities, specialized to support the synchronous paradigm, 2) the definition of an analysis model for temporal properties: the Modular and Hierarchical Time Petri Nets, 3) the transformation from the specification model to the analysis model.
{"title":"From UML to Petri Nets for non functional Property Verification","authors":"F. Mallet, Marie-Agnès Peraldi-Frati, C. André","doi":"10.1109/IES.2006.357475","DOIUrl":"https://doi.org/10.1109/IES.2006.357475","url":null,"abstract":"Real-time embedded architectures consist of software and hardware parts. Meeting non-functional constraints (e.g., real-time constraints) greatly depends on the mappings from the system functionalities to software and hardware components. Thus, there is a strong demand for precise architecture and allocation modeling, amenable to performance analysis. The paper proposes a model-driven approach for the assessment of the quality of allocations of the system functionalities to the architecture. We consider two technical domains: the UML domain for the definition of the model elements, and a non functional property analysis domain, external to UML, used for formal verification. This paper focuses on 1) the specification of expected behavior by UML activities, specialized to support the synchronous paradigm, 2) the definition of an analysis model for temporal properties: the Modular and Hierarchical Time Petri Nets, 3) the transformation from the specification model to the analysis model.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127604957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the current complexity of communication protocols, implementing its layers totally in the kernel of the operating system is too cumbersome, and it does not allow use of the capabilities only available in user space processes. However, building protocols as user space processes must not impair the responsiveness of the communication. Therefore, in this paper we present a layer of a communication protocol, which, due to its complexity, was implemented in a user space process. Lower layers of the protocol are, for responsiveness issues, implemented in the kernel. This protocol was developed to support large-scale power-line communication (PLC) with timing requirements.
{"title":"A Complex Protocol Layer as a linux User-Space Process","authors":"Antonio Barros, F. Pacheco, L. M. Pinho","doi":"10.1109/IES.2006.357478","DOIUrl":"https://doi.org/10.1109/IES.2006.357478","url":null,"abstract":"With the current complexity of communication protocols, implementing its layers totally in the kernel of the operating system is too cumbersome, and it does not allow use of the capabilities only available in user space processes. However, building protocols as user space processes must not impair the responsiveness of the communication. Therefore, in this paper we present a layer of a communication protocol, which, due to its complexity, was implemented in a user space process. Lower layers of the protocol are, for responsiveness issues, implemented in the kernel. This protocol was developed to support large-scale power-line communication (PLC) with timing requirements.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125137406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a hybrid hardware-in-the-loop (HIL) methodology based on both the discrete event system, given by timed automata, and the continuous systems, given by difference equations. The methodology is implemented using an FPGA platform. It guarantees not only the speed enhancement but also the time accuracy and extensibility with no performance loss. Compared to the operating system based platforms, the FPGA platform is able to achieve much faster sampling frequency. Methodology FPGA implementation is generated by using Xilinx System Generator, bit exact toolbox for Matlab/Simulink.
本文提出了一种基于时间自动机给出的离散事件系统和差分方程给出的连续系统的混合硬件在环(HIL)方法。该方法在FPGA平台上实现。它既保证了速度的提高，又保证了时间的准确性和可扩展性，同时又不损失性能。与基于操作系统的平台相比，FPGA平台能够实现更快的采样频率。FPGA实现采用Xilinx System Generator生成，位精确工具箱为Matlab/Simulink。
{"title":"Testing of Hybrid Real-time Systems Using FPGA Platform","authors":"J. Krakora, Z. Hanzálek","doi":"10.1109/IES.2006.357472","DOIUrl":"https://doi.org/10.1109/IES.2006.357472","url":null,"abstract":"This paper presents a hybrid hardware-in-the-loop (HIL) methodology based on both the discrete event system, given by timed automata, and the continuous systems, given by difference equations. The methodology is implemented using an FPGA platform. It guarantees not only the speed enhancement but also the time accuracy and extensibility with no performance loss. Compared to the operating system based platforms, the FPGA platform is able to achieve much faster sampling frequency. Methodology FPGA implementation is generated by using Xilinx System Generator, bit exact toolbox for Matlab/Simulink.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122805005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern DRAM technologies offer power management features for energy consumption optimization. It consists of multi-banking the addressing space instead of monolithic memory. The main advantage in this approach is the capability of setting banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper we investigate how this power management capability can be handled for real-time and multitasking applications. We aim to find, based on the application scheduler, both an efficient allocation of application's tasks to memory banks, and the corresponding memory configuration that lessen the energy consumption: number of banks and the size of each bank. Results show the effectiveness of this approach and the large energy savings.
{"title":"Scheduler-based Multi-Bank Main Memory Configuration for Energy Reduction","authors":"H. Fradj, C. Belleudy, M. Auguin","doi":"10.1109/IES.2006.357460","DOIUrl":"https://doi.org/10.1109/IES.2006.357460","url":null,"abstract":"Modern DRAM technologies offer power management features for energy consumption optimization. It consists of multi-banking the addressing space instead of monolithic memory. The main advantage in this approach is the capability of setting banks in low power modes when they are not accessed, such that only the accessed bank is maintained in active mode. In this paper we investigate how this power management capability can be handled for real-time and multitasking applications. We aim to find, based on the application scheduler, both an efficient allocation of application's tasks to memory banks, and the corresponding memory configuration that lessen the energy consumption: number of banks and the size of each bank. Results show the effectiveness of this approach and the large energy savings.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"3 Suppl N 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116895581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Benjamin Fontan, L. Apvrille, Pierre de Saqui-Sannes, J. Courtiat
TURTLE is a real-time UML profile supported by a toolkit which enables application of formal verification techniques to the analysis, design and deployment phases of systems design trajectory. This paper extends the TURTLE methodology with a requirement capture phase. SysML requirement diagrams are introduced. Temporal requirements (TR) are formally expressed using a dedicated language based on Allen's interval algebra. TRs serve as starting point to automatically synthesize observers and to guide the verification process applied to the TURTLE model of the system. Verification results are automatically collected in traceability matrices. A Hybrid Sport Utility Vehicle serves as example.
{"title":"Real-Time and Embedded System Verification Based on Formal Requirements","authors":"Benjamin Fontan, L. Apvrille, Pierre de Saqui-Sannes, J. Courtiat","doi":"10.1109/IES.2006.357467","DOIUrl":"https://doi.org/10.1109/IES.2006.357467","url":null,"abstract":"TURTLE is a real-time UML profile supported by a toolkit which enables application of formal verification techniques to the analysis, design and deployment phases of systems design trajectory. This paper extends the TURTLE methodology with a requirement capture phase. SysML requirement diagrams are introduced. Temporal requirements (TR) are formally expressed using a dedicated language based on Allen's interval algebra. TRs serve as starting point to automatically synthesize observers and to guide the verification process applied to the TURTLE model of the system. Verification results are automatically collected in traceability matrices. A Hybrid Sport Utility Vehicle serves as example.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Spiga, Mattia Spiga, A. Alimonda, S. Carta, F. Aymerich
Dynamic voltage and frequency scaling (DVFS) has been extensively exploited in the context of hard real-time systems for the development of energy efficient task scheduling algorithms. However, when tasks are memory bounded, further energy improvement could be obtained. In this paper we analyze the effect of memory boundedness in a state-of-the-art energy efficient hard real-time scheduling algorithm, and we propose a new technique to take into account these effects to substantially improve energy efficiency of the scheduling algorithm while still preventing deadline misses. The proposed technique is compared to a state-of-the-art hard real-time scheduling algorithm from energy efficiency viewpoint. Results show an energy reduction from 15% to 90% depending on the amount of memory boundedness of the task.
{"title":"Exploiting Memory-Boundedness in Energy-Efficient Hard Real-Time Scheduling","authors":"M. Spiga, Mattia Spiga, A. Alimonda, S. Carta, F. Aymerich","doi":"10.1109/IES.2006.357463","DOIUrl":"https://doi.org/10.1109/IES.2006.357463","url":null,"abstract":"Dynamic voltage and frequency scaling (DVFS) has been extensively exploited in the context of hard real-time systems for the development of energy efficient task scheduling algorithms. However, when tasks are memory bounded, further energy improvement could be obtained. In this paper we analyze the effect of memory boundedness in a state-of-the-art energy efficient hard real-time scheduling algorithm, and we propose a new technique to take into account these effects to substantially improve energy efficiency of the scheduling algorithm while still preventing deadline misses. The proposed technique is compared to a state-of-the-art hard real-time scheduling algorithm from energy efficiency viewpoint. Results show an energy reduction from 15% to 90% depending on the amount of memory boundedness of the task.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Viejo, M. J. Díaz, A. Millán, E. Ostúa, J. Juan, P. Ruiz-de-Clavijo, David Guerrero Martos
This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance. The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPE interface so that it can be integrated as a standard peripheral of a microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below 1%.
{"title":"Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements","authors":"J. Viejo, M. J. Díaz, A. Millán, E. Ostúa, J. Juan, P. Ruiz-de-Clavijo, David Guerrero Martos","doi":"10.1109/IES.2006.357486","DOIUrl":"https://doi.org/10.1109/IES.2006.357486","url":null,"abstract":"This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance. The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPE interface so that it can be integrated as a standard peripheral of a microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below 1%.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127764966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of system on chip (SoC) is getting more and more complex. One of the challenges is to find out an interconnection topology and a set of architecture parameters which minimize the area and power consumption while satisfying design constraint. The object of this paper is to propose a new design space exploration methodology for network on chip which use (1) hardware emulation for fast performance evaluation (2) actual post synthesis place and route for area results and (3) actual optimal implementation frequency to compute execution time rather than number of cycles. Based on these values, a statistical tool based on principal component analysis brings productivity gains for network on chip designer to quickly select network on chip components appropriate parameters value. Generally speaking the paper introduces fully automatic network on chip implementation cross-layer analysis in an integrated manner. Case studies validate our approach.
{"title":"NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis","authors":"Xinyu Li, O. Hammami","doi":"10.1109/IES.2006.357469","DOIUrl":"https://doi.org/10.1109/IES.2006.357469","url":null,"abstract":"The design of system on chip (SoC) is getting more and more complex. One of the challenges is to find out an interconnection topology and a set of architecture parameters which minimize the area and power consumption while satisfying design constraint. The object of this paper is to propose a new design space exploration methodology for network on chip which use (1) hardware emulation for fast performance evaluation (2) actual post synthesis place and route for area results and (3) actual optimal implementation frequency to compute execution time rather than number of cycles. Based on these values, a statistical tool based on principal component analysis brings productivity gains for network on chip designer to quickly select network on chip components appropriate parameters value. Generally speaking the paper introduces fully automatic network on chip implementation cross-layer analysis in an integrated manner. Case studies validate our approach.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115784888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Rouxel, G. Gogniat, J. Diguet, J. Philippe, C. Moy
This paper describes a fast prototyping tool targeting software radio applications. It is based on the Unified Modeling Language (UML) and combines a Software Defined Radio UML profile for implementing a real MDA approach with EDA tools for multi-level verifications from the type compatibility to the scheduling and memory use analysis over an heterogeneous platform. Our approach relies on performance analysis to improve architecture and application matching thanks to non-functional criteria. The main contributions of our work are the improvement of the original meta-model of the Software Radio UML profile which is currently under standardization and its integration within a unified design framework. From a high abstraction level of a software application we perform extensive verifications and analysis to validate the designer hardware architecture choice and the corresponding implementations.
本文介绍了一种针对软件无线电应用的快速原型工具。它基于统一建模语言(UML)，并结合了软件定义无线电UML概要文件，用于实现真正的MDA方法，以及EDA工具，用于从类型兼容性到异构平台上的调度和内存使用分析的多级验证。我们的方法依靠性能分析来改进体系结构和应用程序匹配，这要归功于非功能标准。我们工作的主要贡献是改进了Software Radio UML概要文件的原始元模型，该模型目前处于标准化之中，并将其集成到一个统一的设计框架中。从软件应用程序的高抽象级别出发，我们执行广泛的验证和分析，以验证设计者硬件架构的选择和相应的实现。
{"title":"System Level Design with UML: a Unified Approach","authors":"S. Rouxel, G. Gogniat, J. Diguet, J. Philippe, C. Moy","doi":"10.1109/IES.2006.357482","DOIUrl":"https://doi.org/10.1109/IES.2006.357482","url":null,"abstract":"This paper describes a fast prototyping tool targeting software radio applications. It is based on the Unified Modeling Language (UML) and combines a Software Defined Radio UML profile for implementing a real MDA approach with EDA tools for multi-level verifications from the type compatibility to the scheduling and memory use analysis over an heterogeneous platform. Our approach relies on performance analysis to improve architecture and application matching thanks to non-functional criteria. The main contributions of our work are the improvement of the original meta-model of the Software Radio UML profile which is currently under standardization and its integration within a unified design framework. From a high abstraction level of a software application we perform extensive verifications and analysis to validate the designer hardware architecture choice and the corresponding implementations.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124490076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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