The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex embedded applications performance requirements. Due to the increasing scale of embedded systems bus-based communication no longer meet bandwidth requirements and therefore networks-on-chip (NoC) are increasingly used to process communication in embedded parallel applications. So far, neither development environments and tools for embedded systems nor profiling and debugging techniques of embedded systems tackled the issue of network on chip monitoring. Due to the complexity of future multiprocessors systems on chip parallel programmers will unavoidably need to be able to get accurate profiles of communication patterns on various network on chip links and this in order to optimize their applications through timing analysis, timing predictability, and real-time scheduling analysis. We propose in this paper a scalable network on chip real time hardware monitoring feedback for multiprocessors systems on chip parallel programmers. Implementation of our scheme for a 2x2 mesh based multiprocessor systems on chip demonstrates the validity of our approach for an image processing application.
{"title":"NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration","authors":"R. B. Mouhoub, O. Hammami","doi":"10.1109/IES.2006.357481","DOIUrl":"https://doi.org/10.1109/IES.2006.357481","url":null,"abstract":"The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex embedded applications performance requirements. Due to the increasing scale of embedded systems bus-based communication no longer meet bandwidth requirements and therefore networks-on-chip (NoC) are increasingly used to process communication in embedded parallel applications. So far, neither development environments and tools for embedded systems nor profiling and debugging techniques of embedded systems tackled the issue of network on chip monitoring. Due to the complexity of future multiprocessors systems on chip parallel programmers will unavoidably need to be able to get accurate profiles of communication patterns on various network on chip links and this in order to optimize their applications through timing analysis, timing predictability, and real-time scheduling analysis. We propose in this paper a scalable network on chip real time hardware monitoring feedback for multiprocessors systems on chip parallel programmers. Implementation of our scheme for a 2x2 mesh based multiprocessor systems on chip demonstrates the validity of our approach for an image processing application.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122718817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a control allocation module with explicit laws has been designed for fast operation and low computational load, so that this algorithm can run in a small processor or microcontroller with limited floating point operation capability. The control allocation method is capable of compensating for actuator faults. Given the appropriate fault detection system, there is no need to redesign the controller, since the control allocator compensates for any fault occurring. A comparison shows that this method yields satisfactory results, provides optimal solutions in some cases, and is simpler and faster than conventional methods.
{"title":"Efficient Control Allocation for Fault Tolerant Embedded Systems on Small Autonomous Aircrafts","authors":"G. Ducard, H. Geering, E. Dumitrescu","doi":"10.1109/IES.2006.357465","DOIUrl":"https://doi.org/10.1109/IES.2006.357465","url":null,"abstract":"In this paper, a control allocation module with explicit laws has been designed for fast operation and low computational load, so that this algorithm can run in a small processor or microcontroller with limited floating point operation capability. The control allocation method is capable of compensating for actuator faults. Given the appropriate fault detection system, there is no need to redesign the controller, since the control allocator compensates for any fault occurring. A comparison shows that this method yields satisfactory results, provides optimal solutions in some cases, and is simpler and faster than conventional methods.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128672257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the deregulation of power market and for providing better services to electric consumers, the current substation should be automated. In the past decade, new communications schemes have been designed and retrofitted into the substations by the utilities to integrate data from relays and intelligent electronic devices (lEDs) and capitalize on the protection, control, metering, fault recording, communication functions available in digital devices. Generally, using station bus to connect all equipments inside the substation, except some primary equipments which are outsider substations such as MV/LV transformer and switchgears. For those outsider equipments, we propose using the REMPLI powerline communication (PLC) technologies to communicate with the substation. The simulation results have shown that the REMPLI PLC network guarantees the substation automation requirements.
{"title":"Powerline Communication System for Monitoring and Supervision of Feeder Equipments for MV Substation Automation","authors":"Liping Lu, Gangyan Li, Yeqiong Song","doi":"10.1109/IES.2006.357474","DOIUrl":"https://doi.org/10.1109/IES.2006.357474","url":null,"abstract":"With the deregulation of power market and for providing better services to electric consumers, the current substation should be automated. In the past decade, new communications schemes have been designed and retrofitted into the substations by the utilities to integrate data from relays and intelligent electronic devices (lEDs) and capitalize on the protection, control, metering, fault recording, communication functions available in digital devices. Generally, using station bus to connect all equipments inside the substation, except some primary equipments which are outsider substations such as MV/LV transformer and switchgears. For those outsider equipments, we propose using the REMPLI powerline communication (PLC) technologies to communicate with the substation. The simulation results have shown that the REMPLI PLC network guarantees the substation automation requirements.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130663170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a complete modeling approach to analyze the thermal behavior of microprocessor-based systems. While most compact modeling approaches require a deep knowledge of the implementation details, our method defines a black box technique which can be applied to different target processors when this detailed information is unknown. The obtained results show high accuracy, applicability and can be easily automated. The proposed methodology has been used to study the impact of code transformations in the thermal behavior of the chip. Finally, the analysis of the thermal effect of the source code modifications can be included in a temperature-aware compiler which minimizes the total temperature of the chip, as well as the temperature gradients, according to these guidelines.
{"title":"Target Independent Thermal Modeling for Embedded Processors","authors":"Cándido Méndez, J. Ayala, M. López-Vallejo","doi":"10.1109/IES.2006.357459","DOIUrl":"https://doi.org/10.1109/IES.2006.357459","url":null,"abstract":"This paper presents a complete modeling approach to analyze the thermal behavior of microprocessor-based systems. While most compact modeling approaches require a deep knowledge of the implementation details, our method defines a black box technique which can be applied to different target processors when this detailed information is unknown. The obtained results show high accuracy, applicability and can be easily automated. The proposed methodology has been used to study the impact of code transformations in the thermal behavior of the chip. Finally, the analysis of the thermal effect of the source code modifications can be included in a temperature-aware compiler which minimizes the total temperature of the chip, as well as the temperature gradients, according to these guidelines.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131049360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we defined a generic architecture for the extraction phase of a multi layer neural network algorithm to be implemented on a Virtex-4 FPGA. This architecture can be applied to any multi layer neural network composed of a given number of layers and a given number of neurons in each layer. In addition this architecture enhances the density of the FPGA by supporting the two concepts of time multiplexing and partial dynamic reconfiguration. Several networks with different sizes were implemented based on this generic architecture. Based on those implementations, we'll analyse the performances of a virtex-4 via a multi layer neural network by analyzing the variation of the minimum period and the number of occupied resources. This work was made in collaboration with the NodBox company (thierry.fargas@nodbox.biz) and Xilinx company (jean-louis.brelet@xilinx.com).
{"title":"FPGA-based generic neural network architecture","authors":"Nicole Chalhoub, F. Muller, M. Auguin","doi":"10.1109/IES.2006.357476","DOIUrl":"https://doi.org/10.1109/IES.2006.357476","url":null,"abstract":"In this paper, we defined a generic architecture for the extraction phase of a multi layer neural network algorithm to be implemented on a Virtex-4 FPGA. This architecture can be applied to any multi layer neural network composed of a given number of layers and a given number of neurons in each layer. In addition this architecture enhances the density of the FPGA by supporting the two concepts of time multiplexing and partial dynamic reconfiguration. Several networks with different sizes were implemented based on this generic architecture. Based on those implementations, we'll analyse the performances of a virtex-4 via a multi layer neural network by analyzing the variation of the minimum period and the number of occupied resources. This work was made in collaboration with the NodBox company (thierry.fargas@nodbox.biz) and Xilinx company (jean-louis.brelet@xilinx.com).","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"138 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125822535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses re configurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as industrial applications. The proposed technique is experimentally evaluated on an 8051 microcontroller using software implemented fault injection (SWIFI). The results show that this technique detects about 90% of the injected control flow errors. The watchdog processor occupied 26% of an Altera Max-7000 FPGA chip logic cells. The performance overhead varies between 42% and 82% depending on the workload used.
{"title":"Transient Error Detection in Embedded Systems Using Reconfigurable Components","authors":"A. Vahdatpour, M. Fazeli, S. Miremadi","doi":"10.1109/IES.2006.357485","DOIUrl":"https://doi.org/10.1109/IES.2006.357485","url":null,"abstract":"In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses re configurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as industrial applications. The proposed technique is experimentally evaluated on an 8051 microcontroller using software implemented fault injection (SWIFI). The results show that this technique detects about 90% of the injected control flow errors. The watchdog processor occupied 26% of an Altera Max-7000 FPGA chip logic cells. The performance overhead varies between 42% and 82% depending on the workload used.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The efficient control of a distributed energy resource (DER) hybrid systems is the key for the optimization of renewable sources used in stand alone generators. The system proposed in this paper is based on a wind/photovoltaic hybrid system with the possibility to integrate a fuel cell as energy backup. The research will result in the production and testing of the hardware prototype of an FPGA based controller for the integrated renewable power generation system. The system proposed uses DK4 (Celoxica) design and modelling software environment based on Handel-C/VHDL programming languages for the rapid prototyping of an FPGA controller.
{"title":"Holistic Modelling of an Integrated Renewable Energy System Controller, Enabling Rapid Hardware Prototyping","authors":"A. Parera-Ruiz, M. Cirstea","doi":"10.1109/IES.2006.357479","DOIUrl":"https://doi.org/10.1109/IES.2006.357479","url":null,"abstract":"The efficient control of a distributed energy resource (DER) hybrid systems is the key for the optimization of renewable sources used in stand alone generators. The system proposed in this paper is based on a wind/photovoltaic hybrid system with the possibility to integrate a fuel cell as energy backup. The research will result in the production and testing of the hardware prototype of an FPGA based controller for the integrated renewable power generation system. The system proposed uses DK4 (Celoxica) design and modelling software environment based on Handel-C/VHDL programming languages for the rapid prototyping of an FPGA controller.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115268574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays industrial embedded systems are increasingly used in safety-critical applications. These embedded systems are based on different hardware platforms, reaching from microcontrollers to programmable logic devices. These different hardware platforms lead to fundamental differences in design. Major differences result from the different hardware architectures and their robustness and reliability as well as on the according differences in the software design process. In this paper, our current work dealing with different hardware platforms used in embedded systems and their influence on the safety and reliability of the overall system is presented.
{"title":"Exploring the Differences of FPGAs and Microcontrollers for their Use in Safety-Critical Embedded Applications","authors":"F. Salewski, S. Kowalewski","doi":"10.1109/IES.2006.357483","DOIUrl":"https://doi.org/10.1109/IES.2006.357483","url":null,"abstract":"Nowadays industrial embedded systems are increasingly used in safety-critical applications. These embedded systems are based on different hardware platforms, reaching from microcontrollers to programmable logic devices. These different hardware platforms lead to fundamental differences in design. Major differences result from the different hardware architectures and their robustness and reliability as well as on the according differences in the software design process. In this paper, our current work dealing with different hardware platforms used in embedded systems and their influence on the safety and reliability of the overall system is presented.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122761690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded systems integrate more and more heterogeneous subsystems. This situation leads to consider on the one hand heterogeneity owing to different formalisms and on the other hand heterogeneity created by platforms in charge of realizing the system. To deal with formalism heterogeneity some modeling frameworks handle different formalisms or project them onto a pivot. Nevertheless these solutions are often not sufficient. This paper presents ongoing works on a development process using Unified Modeling Language (UML) enhanced by a contract approach borrowed from the Interface Automata modeling. The objectives are twofold: (a) provide coherent views of a component along its refinements, (b) specify their interactions.
{"title":"Could UML and Contract tackle heterogeneity?","authors":"F. Lagarde, F. Terrier, C. André","doi":"10.1109/IES.2006.357473","DOIUrl":"https://doi.org/10.1109/IES.2006.357473","url":null,"abstract":"Embedded systems integrate more and more heterogeneous subsystems. This situation leads to consider on the one hand heterogeneity owing to different formalisms and on the other hand heterogeneity created by platforms in charge of realizing the system. To deal with formalism heterogeneity some modeling frameworks handle different formalisms or project them onto a pivot. Nevertheless these solutions are often not sufficient. This paper presents ongoing works on a development process using Unified Modeling Language (UML) enhanced by a contract approach borrowed from the Interface Automata modeling. The objectives are twofold: (a) provide coherent views of a component along its refinements, (b) specify their interactions.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128493334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Nilsson, L. Bengtsson, U. Bilstrup, P. Wiberg, B. Svensson
The use of radio frequency identification systems (RFID) is growing rapidly. Today, mostly "passive" RFID systems are used because no onboard energy source is needed on the transponders. However, "active " RFID with onboard power source gives a new range of opportunities not possible with passive systems. To obtain energy efficiency in an active RFID system a protocol should be designed that is optimized with energy in mind. This paper describes the on-going work of defining and evaluating such a protocol. The protocol's performance in terms of energy efficiency, aggregated throughput, delay, and number of air collisions is evaluated and compared to that of the medium-access layer in 802.15.4 Zigbee, and also to a commercially available protocol from Free2move.
{"title":"Towards an Energy Efficient Protocol for Active RFID","authors":"B. Nilsson, L. Bengtsson, U. Bilstrup, P. Wiberg, B. Svensson","doi":"10.1109/IES.2006.357477","DOIUrl":"https://doi.org/10.1109/IES.2006.357477","url":null,"abstract":"The use of radio frequency identification systems (RFID) is growing rapidly. Today, mostly \"passive\" RFID systems are used because no onboard energy source is needed on the transponders. However, \"active \" RFID with onboard power source gives a new range of opportunities not possible with passive systems. To obtain energy efficiency in an active RFID system a protocol should be designed that is optimized with energy in mind. This paper describes the on-going work of defining and evaluating such a protocol. The protocol's performance in terms of energy efficiency, aggregated throughput, delay, and number of air collisions is evaluated and compared to that of the medium-access layer in 802.15.4 Zigbee, and also to a commercially available protocol from Free2move.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132827677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：