This paper presents a methodology for embedded systems hardware-software co-design, which main objective is to contribute to show Petri nets models adequacy to be used as the underlying formalism amenable to support specification, simulation, verification and implementation, including partitioning into components, co-simulation, co-verification and automatic code generation. The methodology starts grabbing user requirements through UML use-cases, which will be (manually) translated into behavioral sub-models, expressed in one of the following graphical formalisms: state diagrams, hierarchical and concurrent state diagrams, statecharts, sequence diagrams, and Petri nets. Those partial models will be translated into behaviorally equivalent Petri net models, which will be composed in order to obtain the overall system model amenable to support property verification and partitioning into components. For that end a set of (Petri) net operations are referred including net addition and net split. Integration of the tools under development and other common available tools is foreseen as PNML representation is used.
{"title":"Petri nets as supporting formalism within Embedded Systems Co-design","authors":"L. Gomes, Anikó Costa","doi":"10.1109/IES.2006.357468","DOIUrl":"https://doi.org/10.1109/IES.2006.357468","url":null,"abstract":"This paper presents a methodology for embedded systems hardware-software co-design, which main objective is to contribute to show Petri nets models adequacy to be used as the underlying formalism amenable to support specification, simulation, verification and implementation, including partitioning into components, co-simulation, co-verification and automatic code generation. The methodology starts grabbing user requirements through UML use-cases, which will be (manually) translated into behavioral sub-models, expressed in one of the following graphical formalisms: state diagrams, hierarchical and concurrent state diagrams, statecharts, sequence diagrams, and Petri nets. Those partial models will be translated into behaviorally equivalent Petri net models, which will be composed in order to obtain the overall system model amenable to support property verification and partitioning into components. For that end a set of (Petri) net operations are referred including net addition and net split. Integration of the tools under development and other common available tools is foreseen as PNML representation is used.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129974132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Platform-based design (PBD) has been introduced to cope with increasing costs in developing complex embedded systems such as multimedia applications. In this paper, we present a performance-aware model and methodology that provides a comprehensive software and hardware modelling and simulation framework at system-platform level. We apply the methodology for synthesizing and analyzing the performance of several concurrent implementations of a MPEG-4 video encoder on embedded multiprocessor hardware architectures. The analysis allows choosing an implementation that satisfies both the encoding requirements (frame rate) and the environment constraints (available bandwidth).
{"title":"System-Platform Simulation Model Applied to Performance Analysis of Multiprocessor Video Encoding","authors":"I. Assayad, S. Yovine","doi":"10.1109/IES.2006.357458","DOIUrl":"https://doi.org/10.1109/IES.2006.357458","url":null,"abstract":"Platform-based design (PBD) has been introduced to cope with increasing costs in developing complex embedded systems such as multimedia applications. In this paper, we present a performance-aware model and methodology that provides a comprehensive software and hardware modelling and simulation framework at system-platform level. We apply the methodology for synthesizing and analyzing the performance of several concurrent implementations of a MPEG-4 video encoder on embedded multiprocessor hardware architectures. The analysis allows choosing an implementation that satisfies both the encoding requirements (frame rate) and the environment constraints (available bandwidth).","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rapid growth in automotive networked embedded systems has occurred over the past two decades. This leads to complexity, especially in fault diagnosis and testing of such systems. This paper reports a work-in-progress automotive network diagnostic system. The aim is to design a system to monitor and diagnose automotive networks, by using a knowledge-based diagnostic technique. Fault information from several sources is used to build a knowledge base. Network fault codes and possible causes diagnosed by a diagnostic module are then stored in a database. The codes are helpful for manufacturing and service processes. This new diagnostic system would contribute to general automotive diagnosis efficiency as it would help reduce numbers of possible fault causes, thereby, correctly pinpointing faulty devices and shortening diagnostic time.
{"title":"Automotive Network Diagnostic Systems","authors":"J. Suwatthikul, R. McMurran","doi":"10.1109/IES.2006.357470","DOIUrl":"https://doi.org/10.1109/IES.2006.357470","url":null,"abstract":"Rapid growth in automotive networked embedded systems has occurred over the past two decades. This leads to complexity, especially in fault diagnosis and testing of such systems. This paper reports a work-in-progress automotive network diagnostic system. The aim is to design a system to monitor and diagnose automotive networks, by using a knowledge-based diagnostic technique. Fault information from several sources is used to build a knowledge base. Network fault codes and possible causes diagnosed by a diagnostic module are then stored in a database. The codes are helpful for manufacturing and service processes. This new diagnostic system would contribute to general automotive diagnosis efficiency as it would help reduce numbers of possible fault causes, thereby, correctly pinpointing faulty devices and shortening diagnostic time.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Calculation of a navigation solution in a GNSS receiver requires a number of different calculations to be carried out. In this paper, a number of software optimizations that can be used in the calculation of a navigation solution without decreasing the accuracy of the result are presented. Also, some optimizations that appeared to be unsuitable for navigation solution and could not be used are shown. Some attention is put on limited capabilities of embedded hardware (e.g. single-precision FPU) that may be used in GNSS receiver. Software was implemented in ANSI-compatible C language, built for ARM platform and executed on ARM instruction set simulator. Its performance was measured in execution time and estimated Whetstone FLOPs. Presented complexity budget shows the amount of calculations required by each stage of the solution.
{"title":"Performance enhancements for embedded software implementation of GNSS navigation algorithms","authors":"E. Zemskov, J. Nurmi","doi":"10.1109/IES.2006.357487","DOIUrl":"https://doi.org/10.1109/IES.2006.357487","url":null,"abstract":"Calculation of a navigation solution in a GNSS receiver requires a number of different calculations to be carried out. In this paper, a number of software optimizations that can be used in the calculation of a navigation solution without decreasing the accuracy of the result are presented. Also, some optimizations that appeared to be unsuitable for navigation solution and could not be used are shown. Some attention is put on limited capabilities of embedded hardware (e.g. single-precision FPU) that may be used in GNSS receiver. Software was implemented in ANSI-compatible C language, built for ARM platform and executed on ARM instruction set simulator. Its performance was measured in execution time and estimated Whetstone FLOPs. Presented complexity budget shows the amount of calculations required by each stage of the solution.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117054979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a model and method to determine the temporal distribution of task activations occurring within an event driven real time system. As real time systems even in safety critical applications are becoming increasingly complex, it becomes increasingly important to get a better understanding of the activity within these systems. The event stream model is a powerful yet efficient way to describe the temporal occurrence of events within a system. Real time analysis can be elegantly performed using given event streams, however it has so far not been investigated how the event streams themselves can be acquired. By calculating the temporal distribution of task activations within a system, a more accurate description of the timing behavior of a system is possible which in the end can lead to a save and cost efficient estimate on the hardware required for the system.
{"title":"Analyzing the Timing Characteristics of Task Activations","authors":"F. Bodmann, K. Albers, F. Slomka","doi":"10.1109/IES.2006.357461","DOIUrl":"https://doi.org/10.1109/IES.2006.357461","url":null,"abstract":"We propose a model and method to determine the temporal distribution of task activations occurring within an event driven real time system. As real time systems even in safety critical applications are becoming increasingly complex, it becomes increasingly important to get a better understanding of the activity within these systems. The event stream model is a powerful yet efficient way to describe the temporal occurrence of events within a system. Real time analysis can be elegantly performed using given event streams, however it has so far not been investigated how the event streams themselves can be acquired. By calculating the temporal distribution of task activations within a system, a more accurate description of the timing behavior of a system is possible which in the end can lead to a save and cost efficient estimate on the hardware required for the system.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116096636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Computational geometry algorithms are more and more frequently used in industrial embedded systems. These new applications require not only highly efficient implementations that run with limited computational resources, but also algorithms that are capable to robustly handle all geometric situations in a consistent way. In this paper, we present the adaptation and implementation of a map overlay algorithm, which originates from the area of geographical information systems. Besides the adaptation to an embedded platform, mainly two problems have to be tackled: First, safe results must be computed with limited precision arithmetic and second, map data must be adequately simplified to meet on the one hand real-time requirements, and on the other hand robustness criteria.
{"title":"Efficient Map Overlay for Safety-Critical Embedded Systems","authors":"J. Brandt, K. Schneider","doi":"10.1109/IES.2006.357462","DOIUrl":"https://doi.org/10.1109/IES.2006.357462","url":null,"abstract":"Computational geometry algorithms are more and more frequently used in industrial embedded systems. These new applications require not only highly efficient implementations that run with limited computational resources, but also algorithms that are capable to robustly handle all geometric situations in a consistent way. In this paper, we present the adaptation and implementation of a map overlay algorithm, which originates from the area of geographical information systems. Besides the adaptation to an embedded platform, mainly two problems have to be tackled: First, safe results must be computed with limited precision arithmetic and second, map data must be adequately simplified to meet on the one hand real-time requirements, and on the other hand robustness criteria.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124847446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm, proposed for 4G communication systems. We used two pipelined arithmetic libraries based on the logarithmic number system or the floating-point number system, using the widely known IEEE format for the floating-point calculations required in the algorithm. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, important part of the article is devoted to the reduction of the problem size.
{"title":"Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm","authors":"P. Šůcha, Z. Hanzálek, A. Hermanek, J. Schier","doi":"10.1109/IES.2006.357480","DOIUrl":"https://doi.org/10.1109/IES.2006.357480","url":null,"abstract":"This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm, proposed for 4G communication systems. We used two pipelined arithmetic libraries based on the logarithmic number system or the floating-point number system, using the widely known IEEE format for the floating-point calculations required in the algorithm. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, important part of the article is devoted to the reduction of the problem size.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134347896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work we take a control theoretic approach to the dynamic voltage/frequency scaling (DVS) in a MPSoC architecture with mixed pipelined/parallel processing. The aim is that of minimizing energy consumption with throughput guarantees. Theoretical analysis and experiments, carried out on a cycle-accurate, energy-aware, multiprocessor simulation platform, are provided. We give a dynamic model of the system behavior on the basis of which we synthesize a non-linear feedback controller for the run-time adjustment the frequencies of the processing stages. We compare, from an energy consumption viewpoint, the proposed feedback approaches with local DVS policies.
{"title":"Non-Linear Feedback Control for Energy Efficient On-Chip Streaming Computation","authors":"A. Alimonda, S. Carta, A. Acquaviva, A. Pisano","doi":"10.1109/IES.2006.357456","DOIUrl":"https://doi.org/10.1109/IES.2006.357456","url":null,"abstract":"In this work we take a control theoretic approach to the dynamic voltage/frequency scaling (DVS) in a MPSoC architecture with mixed pipelined/parallel processing. The aim is that of minimizing energy consumption with throughput guarantees. Theoretical analysis and experiments, carried out on a cycle-accurate, energy-aware, multiprocessor simulation platform, are provided. We give a dynamic model of the system behavior on the basis of which we synthesize a non-linear feedback controller for the run-time adjustment the frequencies of the processing stages. We compare, from an energy consumption viewpoint, the proposed feedback approaches with local DVS policies.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124832572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ciordas, K. Goossens, T. Basten, A. Radulescu, Andre Boon
Networks-on-chip (NoC) are a scalable interconnect solution to multiprocessor systems on chip (MPSoC). NoCs transport data in packets which are fragments of transactions, such as read and write actions of IPs. For debug purposes, reconstructing transactions at run-time is essential. Run-time analysis of the NoC behavior at transaction level makes the complete MPSoC easier to understand. We present a NoC analyzer able to monitor NoC transactions at run-time. The proposed hardware transaction monitor is able to reconstruct on-chip, at run-time, NoC transactions from bit-level intercepted router link communication. Four NoC analyzer modes are detailed raising the abstraction level gradually from physical raw to logical connection-based, transaction-based and abstract transaction event-based. Each mode is analyzed for area and bandwidth in an experimental setup based on several AEligthereal NoC designs. A transaction monitor has an area cost of 0.026 mm2 in a 0.13 mum CMOS technology, and for several MPEG/audio case studies, the entire monitoring system adds an average of 5% to the NoC area. We show the versatility of our NoC analyzer by run-time monitoring user connections and the Configuration Master IP in the NoC.
片上网络(NoC)是多处理器片上系统(MPSoC)的可扩展互连解决方案。noc以数据包的形式传输数据，这些数据包是事务的片段，例如ip的读和写动作。出于调试目的，在运行时重构事务是必不可少的。在事务级别的NoC行为的运行时分析使完整的MPSoC更容易理解。我们提出了一个能够在运行时监视NoC事务的NoC分析器。所提出的硬件事务监控器能够在运行时从位级截获的路由器链路通信重建片上NoC事务。详细介绍了四种NoC分析模式，将抽象层次从物理原始逐步提高到基于逻辑连接、基于事务和基于抽象事务事件。在实验装置中，分析了基于几种aeligereal NoC设计的每种模式的面积和带宽。在0.13 mm CMOS技术中，事务监控器的面积成本为0.026 mm2，对于一些MPEG/音频案例研究，整个监控系统平均增加了5%的NoC面积。通过运行时监视用户连接和NoC中的配置主IP，我们展示了NoC分析器的多功能性。
{"title":"Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective","authors":"C. Ciordas, K. Goossens, T. Basten, A. Radulescu, Andre Boon","doi":"10.1109/IES.2006.357464","DOIUrl":"https://doi.org/10.1109/IES.2006.357464","url":null,"abstract":"Networks-on-chip (NoC) are a scalable interconnect solution to multiprocessor systems on chip (MPSoC). NoCs transport data in packets which are fragments of transactions, such as read and write actions of IPs. For debug purposes, reconstructing transactions at run-time is essential. Run-time analysis of the NoC behavior at transaction level makes the complete MPSoC easier to understand. We present a NoC analyzer able to monitor NoC transactions at run-time. The proposed hardware transaction monitor is able to reconstruct on-chip, at run-time, NoC transactions from bit-level intercepted router link communication. Four NoC analyzer modes are detailed raising the abstraction level gradually from physical raw to logical connection-based, transaction-based and abstract transaction event-based. Each mode is analyzed for area and bandwidth in an experimental setup based on several AEligthereal NoC designs. A transaction monitor has an area cost of 0.026 mm2 in a 0.13 mum CMOS technology, and for several MPEG/audio case studies, the entire monitoring system adds an average of 5% to the NoC area. We show the versatility of our NoC analyzer by run-time monitoring user connections and the Configuration Master IP in the NoC.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130393401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we put forward an approach to optimize Java applications for embedded systems. Its principle is to use a specific profiler dedicated to optimization. The profiler takes as an input a Java Application and provides the best possible sequence of optimization techniques. Strategy resolution goes through the study of the fundamental optimization techniques and the exploration of the research space that they compose.
{"title":"Profile-Based Optimization for Embedded Java Applications","authors":"Karim Ammous, N. Benameur, M. Abed","doi":"10.1109/IES.2006.357457","DOIUrl":"https://doi.org/10.1109/IES.2006.357457","url":null,"abstract":"In this paper, we put forward an approach to optimize Java applications for embedded systems. Its principle is to use a specific profiler dedicated to optimization. The profiler takes as an input a Java Application and provides the best possible sequence of optimization techniques. Strategy resolution goes through the study of the fundamental optimization techniques and the exploration of the research space that they compose.","PeriodicalId":412676,"journal":{"name":"2006 International Symposium on Industrial Embedded Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124959953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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