The digital and analog performance of 2-D vdW-FETs has been investigated using the quantum-transport simulations. This work also presented a performance comparison between 2-D vdW-FETs and Si-MOSFET. It has found that MoS2 can deliver lower power consumption and higher speed for geometries corresponding to those of the 2028 node of the 2013 ITRS. On the other hand, WS2 -FET can provide better gate controllability, higher speed, and lower power consumption over 2-D vdW-FET for L g > 5 nm. However, in the deep nanometer range, the analog and digital performance metrics of 2-D vdW-FETs have found comparable to Si-MOSFET, even the intrinsic PDP of MoS2 - and WS2 -FET is marginally smaller than that of Si-MOSFET. Thus, single -layer TMD-FETs are certainly not the best option for post-silicon electronic, but the optimization of material geometry and an effective device design strategy can allow better gate controllability and performance improvement. Future studies in 2-D vdW-FETs should focus on understanding the interplay of scattering mechanisms due to substrate interactions or impurities to recognize roadblocks for next-generation flexible and transparent electronics.
{"title":"Two-dimensional material-based field-effect transistors for post-silicon electronics","authors":"Brajesh Rawat, R. Paily","doi":"10.1049/pbcs073f_ch8","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch8","url":null,"abstract":"The digital and analog performance of 2-D vdW-FETs has been investigated using the quantum-transport simulations. This work also presented a performance comparison between 2-D vdW-FETs and Si-MOSFET. It has found that MoS2 can deliver lower power consumption and higher speed for geometries corresponding to those of the 2028 node of the 2013 ITRS. On the other hand, WS2 -FET can provide better gate controllability, higher speed, and lower power consumption over 2-D vdW-FET for L g > 5 nm. However, in the deep nanometer range, the analog and digital performance metrics of 2-D vdW-FETs have found comparable to Si-MOSFET, even the intrinsic PDP of MoS2 - and WS2 -FET is marginally smaller than that of Si-MOSFET. Thus, single -layer TMD-FETs are certainly not the best option for post-silicon electronic, but the optimization of material geometry and an effective device design strategy can allow better gate controllability and performance improvement. Future studies in 2-D vdW-FETs should focus on understanding the interplay of scattering mechanisms due to substrate interactions or impurities to recognize roadblocks for next-generation flexible and transparent electronics.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128864880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells implemented at 45 nm technology node which are suitable for subthreshold operation. For quick comparison, Figure 3.45 shows the comparative design space exploration (DSE) chart of SRAM cells at 45 nm technology, respectively. The thorough analyses on the impacts of read stability, write ability, average write delay, average read delay and leakage power consumption in hold mode have been summarized in Table 3.14. The proposed memory cells exhibit improvement in performance over C6T.
{"title":"Low-voltage, low-power SRAM circuits using subthreshold design technique","authors":"Anu Gupta, Priya Gupta, Abhijit R. Asati","doi":"10.1049/pbcs073f_ch3","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch3","url":null,"abstract":"This chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells implemented at 45 nm technology node which are suitable for subthreshold operation. For quick comparison, Figure 3.45 shows the comparative design space exploration (DSE) chart of SRAM cells at 45 nm technology, respectively. The thorough analyses on the impacts of read stability, write ability, average write delay, average read delay and leakage power consumption in hold mode have been summarized in Table 3.14. The proposed memory cells exhibit improvement in performance over C6T.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127063303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Intel declared 2016 as the end of Moore's prediction. Researchers and academicians are exploring other alternatives to fulfill the latency between the processor and memory system. A universal memory is required that can be used at the various levels of memory hierarchy. STT-MRAM has shown the promising features to be used at various levels of memory hierarchy. In this chapter, we discussed the GMR, TMR, and STT as the basic phenomena required for STT-MRAM reading and writing. Conversion of charge current to spin-polarized current is explained with the help of Bloch states of different symmetries. I-MTJ and P-MTJ are explained using key performance parameters such as thermal stability and critical current. Working of STT-MRAM bit cell is discussed using NMOS transistor as an access device. Framework for low power hybrid MTJ/CMOS circuits is explained using PCSA, CMOS logic tree, and nonvolatile input store in terms of relative magnetization state of MTJs. STT-MRAM faces the challenges of high write energy, reliability, and read disturbance due to common read and write path. To mitigate these issues, SOT-based device and fast-switching mechanism VCMA has been suggested. Finally, based on the performance of STT-MRAM, it can be projected that low-power operations can be achieved using STT-MRAM as a working memory. Further, high-speed and low-power operations can be attained with hybrid MTJ/CMOS nonvolatile core circuits. The recent developments in the spintronics field have opened the door for energy-saving and high-performance electronics from device level to circuit level.
{"title":"Spintronics memory and logic: an efficient alternative to CMOS technology","authors":"V. Nehra, B. Kaushik","doi":"10.1049/pbcs073f_ch10","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch10","url":null,"abstract":"Intel declared 2016 as the end of Moore's prediction. Researchers and academicians are exploring other alternatives to fulfill the latency between the processor and memory system. A universal memory is required that can be used at the various levels of memory hierarchy. STT-MRAM has shown the promising features to be used at various levels of memory hierarchy. In this chapter, we discussed the GMR, TMR, and STT as the basic phenomena required for STT-MRAM reading and writing. Conversion of charge current to spin-polarized current is explained with the help of Bloch states of different symmetries. I-MTJ and P-MTJ are explained using key performance parameters such as thermal stability and critical current. Working of STT-MRAM bit cell is discussed using NMOS transistor as an access device. Framework for low power hybrid MTJ/CMOS circuits is explained using PCSA, CMOS logic tree, and nonvolatile input store in terms of relative magnetization state of MTJs. STT-MRAM faces the challenges of high write energy, reliability, and read disturbance due to common read and write path. To mitigate these issues, SOT-based device and fast-switching mechanism VCMA has been suggested. Finally, based on the performance of STT-MRAM, it can be projected that low-power operations can be achieved using STT-MRAM as a working memory. Further, high-speed and low-power operations can be attained with hybrid MTJ/CMOS nonvolatile core circuits. The recent developments in the spintronics field have opened the door for energy-saving and high-performance electronics from device level to circuit level.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115541657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Here, we have presented several CM structures, summary of which is presented in Table 1.1. One can select an appropriate CM for a particular application. For example in low -voltage application, simple CM, wide -swing CM and enhanced output impedance CM can be selected because they require low compliance voltages at the output node. However, the output impedance of the simple CM is too low, and it may not be possible to use these mirrors in most of the application. Thus, the choice falls on using wide -swing and enhanced output impedance CM. Since the structure of enhanced output impedance CM is complicated, generally their use is restricted to special type of applications, where their use cannot be avoided. Often we require tight matching between input and output currents. This in turn requires tight matching between the device dimensions. This problem of device mismatches, however, has not been addressed. Further the current obtainable from the CMs should be invariant to the supply voltages and/or temperatures changes between some specified limits, which have not been discussed here.
{"title":"Low-voltage analog signal processing","authors":"Ahlad Kumar, S. Rajput","doi":"10.1049/pbcs073f_ch1","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch1","url":null,"abstract":"Here, we have presented several CM structures, summary of which is presented in Table 1.1. One can select an appropriate CM for a particular application. For example in low -voltage application, simple CM, wide -swing CM and enhanced output impedance CM can be selected because they require low compliance voltages at the output node. However, the output impedance of the simple CM is too low, and it may not be possible to use these mirrors in most of the application. Thus, the choice falls on using wide -swing and enhanced output impedance CM. Since the structure of enhanced output impedance CM is complicated, generally their use is restricted to special type of applications, where their use cannot be avoided. Often we require tight matching between input and output currents. This in turn requires tight matching between the device dimensions. This problem of device mismatches, however, has not been addressed. Further the current obtainable from the CMs should be invariant to the supply voltages and/or temperatures changes between some specified limits, which have not been discussed here.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133824627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Raman, Deep Shekhar, Ravi Ranjan, Suchitra Kumari
Using conventional memory technologies, for example, static random access memory (RAM) (SRAM), dynamic RAM (DRAM) and flash memory, it is difficult to fulfill the market requirements for higher density and lower power dissipation [1]. Therefore, semiconductor organizations are thinking that it is difficult to supply the expanding market interest for the higher density and lower power nonvolatile memories [2]. The recent invention of memristor device has given hope to semiconductor organizations by offering a less demanding approach to expand the density by utilizing the current fabrication technology [3]. This is conceivable on the grounds that memristor devices just require two terminals to work, which utilize less wafer space, reduce the complexity of circuit interconnections and encourage highdensity integration when used as a part of crossbar structures [4-7]. Besides all these features of memristor, it also has some additional characteristics like low power and non-volatility [8]. But the main limitation of the memristor-based memory cell is its slow write time access [9]. Transmission gate is capable of providing rail-to-rail swing and can easily pass both logic “0” and logic “1” [10]. These advantages help to overcome the problem of slow write time access of memristor. The objective of this chapter is to understand what a memristor is and how can a memristor be modeled for its current-voltage (I-V) characteristics. Further, this chapter deals with the concepts of transmission gates, then using the designed memristor and transmission gates, a DRAM cell was designed. The designed memory cell was simulated using HSPICE tool. The result shows that the memristor-based DRAM cell can replace the conventional memory cell in future to achieve higher density and lower power dissipation.
{"title":"Design and analysis of memristor-based DRAM cell for low-power application","authors":"A. Raman, Deep Shekhar, Ravi Ranjan, Suchitra Kumari","doi":"10.1049/pbcs073f_ch4","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch4","url":null,"abstract":"Using conventional memory technologies, for example, static random access memory (RAM) (SRAM), dynamic RAM (DRAM) and flash memory, it is difficult to fulfill the market requirements for higher density and lower power dissipation [1]. Therefore, semiconductor organizations are thinking that it is difficult to supply the expanding market interest for the higher density and lower power nonvolatile memories [2]. The recent invention of memristor device has given hope to semiconductor organizations by offering a less demanding approach to expand the density by utilizing the current fabrication technology [3]. This is conceivable on the grounds that memristor devices just require two terminals to work, which utilize less wafer space, reduce the complexity of circuit interconnections and encourage highdensity integration when used as a part of crossbar structures [4-7]. Besides all these features of memristor, it also has some additional characteristics like low power and non-volatility [8]. But the main limitation of the memristor-based memory cell is its slow write time access [9]. Transmission gate is capable of providing rail-to-rail swing and can easily pass both logic “0” and logic “1” [10]. These advantages help to overcome the problem of slow write time access of memristor. The objective of this chapter is to understand what a memristor is and how can a memristor be modeled for its current-voltage (I-V) characteristics. Further, this chapter deals with the concepts of transmission gates, then using the designed memristor and transmission gates, a DRAM cell was designed. The designed memory cell was simulated using HSPICE tool. The result shows that the memristor-based DRAM cell can replace the conventional memory cell in future to achieve higher density and lower power dissipation.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"2 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133742461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It has been found that the proposed PLL design results in reduced lock time and reference spur while maintaining stable closed -loop operation. Composite PFD provides high gain and high loop band width (BW) during lock -in and lower loop BW after getting locked -in resulting in improvement in lock -in and noise characteristics. NL-PFD helps in eliminating blind zone, and linear PFD helps in eliminating dead zone while suppressing unwanted glitches completely from the output of the PFDs resulting in reduced reference spur. Charge pump and LF topology have been developed so as to maintain constant phase margin to ensure stability during tracking and after lock -in. A prototype of PLL operating at 2.56 GHz developed with 180 nm CMOS process is found to achieve reference spur of -71.4 dB c at 20 MHz offset.
研究发现，所提出的锁相环设计减少了锁相时间和参考杂散，同时保持了稳定的闭环运行。复合PFD在锁相期间提供高增益和高环路带宽(BW)，锁相后提供更低的环路带宽，从而改善了锁相和噪声特性。NL-PFD有助于消除盲区，线性PFD有助于消除死区，同时完全抑制PFD输出中不必要的小故障，从而减少参考杂散。电荷泵和LF拓扑结构的发展是为了保持恒定的相位裕度，以确保跟踪期间和锁定后的稳定性。采用180 nm CMOS工艺开发的2.56 GHz锁相环原型在20mhz偏移时实现了-71.4 dB c的参考杂散。
{"title":"Composite PFD based low-power, low noise, fast lock-in PLL","authors":"B. Kailath, Kottampara Kuppalath Majeed","doi":"10.1049/pbcs073f_ch6","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch6","url":null,"abstract":"It has been found that the proposed PLL design results in reduced lock time and reference spur while maintaining stable closed -loop operation. Composite PFD provides high gain and high loop band width (BW) during lock -in and lower loop BW after getting locked -in resulting in improvement in lock -in and noise characteristics. NL-PFD helps in eliminating blind zone, and linear PFD helps in eliminating dead zone while suppressing unwanted glitches completely from the output of the PFDs resulting in reduced reference spur. Charge pump and LF topology have been developed so as to maintain constant phase margin to ensure stability during tracking and after lock -in. A prototype of PLL operating at 2.56 GHz developed with 180 nm CMOS process is found to achieve reference spur of -71.4 dB c at 20 MHz offset.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125562823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this book chapter, a brief introduction is provided to CNTs, its material science, modelling, simulation and circuit application. CNTs are explored from electronic properties as the nature of conduction, i.e., metallic and semiconducting. Chirality is explained, which is responsible for basic parameters calculations like diameter and bandgap. Considering the excellent characteristics of CNT, how they are used as channel materials in MOSFETs is discussed along with the type of CNTFET. The physics behind the working of CNTFET is explained for every type along with advantages and disadvantages of device type. Since CNTFETs have many challenges for future devices, the most important challenge of doping is discussed along with the novel solution, i.e., electrostatic doping. The concept of electrostatic doping is explained with the help of a band diagram as how the biases at polarity gates are used to shift the bands the same as in conventional doping. The characteristics of an ED device are compared with a conventional doped device in order to get better understanding and advantage of the device. The only available benchmark simulation tool for CNTFETs is discussed along with the model used in calculations of drain current. Also the different types of CNTFETs are simulated in this tool, and the characteristics are shown. Apart from conventional CNTFET, ED CNTFET is also simulated in the tool in order to check the results. Along with numerical tool for simulation, the various approaches that can be used to model the device are discussed. The equations are explained with device physics for both conventional CNTFET and ED CNTFET. Lastly, the circuit applications are discussed ranging from analog to digital applications.
{"title":"CNTFETs: modelling and circuit design","authors":"Amandeep Singh, M. Khosla, B. Raj","doi":"10.1049/pbcs073f_ch13","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch13","url":null,"abstract":"In this book chapter, a brief introduction is provided to CNTs, its material science, modelling, simulation and circuit application. CNTs are explored from electronic properties as the nature of conduction, i.e., metallic and semiconducting. Chirality is explained, which is responsible for basic parameters calculations like diameter and bandgap. Considering the excellent characteristics of CNT, how they are used as channel materials in MOSFETs is discussed along with the type of CNTFET. The physics behind the working of CNTFET is explained for every type along with advantages and disadvantages of device type. Since CNTFETs have many challenges for future devices, the most important challenge of doping is discussed along with the novel solution, i.e., electrostatic doping. The concept of electrostatic doping is explained with the help of a band diagram as how the biases at polarity gates are used to shift the bands the same as in conventional doping. The characteristics of an ED device are compared with a conventional doped device in order to get better understanding and advantage of the device. The only available benchmark simulation tool for CNTFETs is discussed along with the model used in calculations of drain current. Also the different types of CNTFETs are simulated in this tool, and the characteristics are shown. Apart from conventional CNTFET, ED CNTFET is also simulated in the tool in order to check the results. Along with numerical tool for simulation, the various approaches that can be used to model the device are discussed. The equations are explained with device physics for both conventional CNTFET and ED CNTFET. Lastly, the circuit applications are discussed ranging from analog to digital applications.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121278806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this chapter, the principle of operation of tunnel FET is discussed. Existing models and modified structures including gate, source and drain engineering are explored and investigated. It depicts the application of tunnel FET in a digital circuit and as biosensor. It is found that TFET has reduced power consumption and can be used in low-power applications. Further, it acts as a better biosensor.
{"title":"Design of a novel tunnel FET for low-power applications","authors":"B. Bhowmick","doi":"10.1049/pbcs073f_ch5","DOIUrl":"https://doi.org/10.1049/pbcs073f_ch5","url":null,"abstract":"In this chapter, the principle of operation of tunnel FET is discussed. Existing models and modified structures including gate, source and drain engineering are explored and investigated. It depicts the application of tunnel FET in a digital circuit and as biosensor. It is found that TFET has reduced power consumption and can be used in low-power applications. Further, it acts as a better biosensor.","PeriodicalId":413845,"journal":{"name":"VLSI and Post-CMOS Electronics. Volume 1: Design, modelling and simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130600107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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