Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962094
J. Mathew, M. Ottavi, Yunfan Yang, D. Pradhan
Memristor is an emerging non-volatile memory device that features smaller size and hybrid memristor/CMOS integration, which maximizes the advantages of high density and versatility. In this paper we utilize the memristor as weights and its state change behavior to capture some of the potential faults in a system. Photovoltaic arrays are taken as an example for the study. We will demonstrate that the state variations can be mapped into a timing which can be used as useful information for behavior of the system under measurement. Empirical studies are carried out using Spice based simulations to investigate into the impact of biasing and threshold voltages on timing behavior. Underpinning these studies, a relationship between input voltage and memristor state transition is proposed and extensively validated through further simulations to identify specific faulty behavior.
{"title":"Using memristor state change behavior to identify faults in photovoltaic arrays","authors":"J. Mathew, M. Ottavi, Yunfan Yang, D. Pradhan","doi":"10.1109/DFT.2014.6962094","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962094","url":null,"abstract":"Memristor is an emerging non-volatile memory device that features smaller size and hybrid memristor/CMOS integration, which maximizes the advantages of high density and versatility. In this paper we utilize the memristor as weights and its state change behavior to capture some of the potential faults in a system. Photovoltaic arrays are taken as an example for the study. We will demonstrate that the state variations can be mapped into a timing which can be used as useful information for behavior of the system under measurement. Empirical studies are carried out using Spice based simulations to investigate into the impact of biasing and threshold voltages on timing behavior. Underpinning these studies, a relationship between input voltage and memristor state transition is proposed and extensively validated through further simulations to identify specific faulty behavior.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127389108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962061
Wei Wei, F. Lombardi, K. Namba
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.
{"title":"Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance","authors":"Wei Wei, F. Lombardi, K. Namba","doi":"10.1109/DFT.2014.6962061","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962061","url":null,"abstract":"This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage. Simulation of these cells shows that their operation has a very high SEU tolerance, the charges in the nodes of the circuits for non-volatile storage and gate leakage current reduction have very high values, thus ensuring that a SEU will highly unlike affect the correct functions. A SER analysis of these cells is also pursued. An extensive evaluation and comparison of different schemes are presented.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962071
C. Zheng, Shuai Wang
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and transistor budget, protecting them against soft errors is of paramount importance. Recent research has focused on the characterization and optimization for the reliability of data caches in single-core processors. As the mainstream processors enter the multi-/many-core era, the area share of the on-chip caches keeps increasing, which makes them more vulnerable to soft errors. However, few research work has studied the vulnerability of the on-chip caches in the context of the cache coherence protocols. In this work, we propose to characterize the soft error vulnerability of the L1 data cache in chip-multiprocessors (CMPs) under the influence of different cache coherence protocols. This study aims to provide insights into cache vulnerability behaviors in CMPs as well as guidance in designing reliable cache coherence protocols. Furthermore, an early-invalidation scheme is proposed to reduce the overall vulnerability factor of the data caches in CMPs. Benchmarking is carried out to showcase the effectiveness of our approach.
{"title":"Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors","authors":"C. Zheng, Shuai Wang","doi":"10.1109/DFT.2014.6962071","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962071","url":null,"abstract":"Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and transistor budget, protecting them against soft errors is of paramount importance. Recent research has focused on the characterization and optimization for the reliability of data caches in single-core processors. As the mainstream processors enter the multi-/many-core era, the area share of the on-chip caches keeps increasing, which makes them more vulnerable to soft errors. However, few research work has studied the vulnerability of the on-chip caches in the context of the cache coherence protocols. In this work, we propose to characterize the soft error vulnerability of the L1 data cache in chip-multiprocessors (CMPs) under the influence of different cache coherence protocols. This study aims to provide insights into cache vulnerability behaviors in CMPs as well as guidance in designing reliable cache coherence protocols. Furthermore, an early-invalidation scheme is proposed to reduce the overall vulnerability factor of the data caches in CMPs. Benchmarking is carried out to showcase the effectiveness of our approach.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114486939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962091
H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi
Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.
{"title":"A data recomputation approach for reliability improvement of scratchpad memory in embedded systems","authors":"H. Sayadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, S. Miremadi","doi":"10.1109/DFT.2014.6962091","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962091","url":null,"abstract":"Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and minimum overheads. This proposed data recomputation algorithm recomputes the correct value whenever an error is detected in the SPM. The simulation results show that the proposed algorithm significantly reduces the vulnerability of SPM from 91.7% to 8.4%. Moreover, the proposed algorithm imposes no area overhead and no hardware modification, meanwhile its performance overhead is less than 1%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131453740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962086
M. Ebrahimi, Junshi Wang, Letian Huang, M. Daneshtalab, A. Jantsch
A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.
{"title":"Rescuing healthy cores against disabled routers","authors":"M. Ebrahimi, Junshi Wang, Letian Huang, M. Daneshtalab, A. Jantsch","doi":"10.1109/DFT.2014.6962086","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962086","url":null,"abstract":"A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"4 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132968868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962060
P. Junsangsri, Jie Han, F. Lombardi
This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold resistances found by the proposed scheme drift with time, thus providing an efficient and viable approach when the number of levels increases. A detailed analysis of the proposed level separation and threshold resistance selection is pursued. The impact of different parameters (such as the write region and the number of cell in a row) is assessed with respect to the generation of the percentage accuracy. The proposed approach results in a substantial improvement in performance compared with existing schemes found in the technical literature.
{"title":"A system-level scheme for resistance drift tolerance of a multilevel phase change memory","authors":"P. Junsangsri, Jie Han, F. Lombardi","doi":"10.1109/DFT.2014.6962060","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962060","url":null,"abstract":"This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row of PCM cells as reference. The threshold resistances found by the proposed scheme drift with time, thus providing an efficient and viable approach when the number of levels increases. A detailed analysis of the proposed level separation and threshold resistance selection is pursued. The impact of different parameters (such as the write region and the number of cell in a row) is assessed with respect to the generation of the percentage accuracy. The proposed approach results in a substantial improvement in performance compared with existing schemes found in the technical literature.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131994048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962067
Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, N. Bagherzadeh
A reliable Three Dimensional Network-on-Chip (3D NoC) is required for future many-core systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better performance and lower power consumption. Inductive TSV coupling has large disruptive effects on Signal Integrity (SI) and transmission delay. In this paper, TSV inductive coupling is analyzed based on technology process, TSV length, and TSV radius for a range of frequencies. A classification of inductive coupling voltage is presented for different TSV configurations. A novel coding technique is devised to mitigate the inductive coupling effects by adjusting the current flow pattern. Simulations for a 4×8 TSV matrix show 23% coupled voltage mitigation, imposing 12.5% information redundancy.
{"title":"TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip","authors":"Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, N. Bagherzadeh","doi":"10.1109/DFT.2014.6962067","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962067","url":null,"abstract":"A reliable Three Dimensional Network-on-Chip (3D NoC) is required for future many-core systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better performance and lower power consumption. Inductive TSV coupling has large disruptive effects on Signal Integrity (SI) and transmission delay. In this paper, TSV inductive coupling is analyzed based on technology process, TSV length, and TSV radius for a range of frequencies. A classification of inductive coupling voltage is presented for different TSV configurations. A novel coding technique is devised to mitigate the inductive coupling effects by adjusting the current flow pattern. Simulations for a 4×8 TSV matrix show 23% coupled voltage mitigation, imposing 12.5% information redundancy.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133805899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962062
T. Iwagaki, Tatsuya Nakaso, R. Ohkubo, H. Ichihara, Tomoo Inoue
As the advance in semiconductor technologies, transient faults caused by particle strike in combinational logic, so-called SETs, have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle. This paper presents a scheduling algorithm in high-level synthesis of long duration transient fault tolerant datapaths. On the basis of the properties of operational units for error correction and detection in behaviorally tripled module systems, we introduce the concept of forces among operations in unscheduled data-flow graphs, and propose a scheduling algorithm based on well-known force-directed scheduling. Experimental results show that the proposed scheduling algorithm can derive multi-cycle fault tolerant datapaths with small hardware resources compared with simply-tripled datapaths.
{"title":"Scheduling algorithm in datapath synthesis for long duration transient fault tolerance","authors":"T. Iwagaki, Tatsuya Nakaso, R. Ohkubo, H. Ichihara, Tomoo Inoue","doi":"10.1109/DFT.2014.6962062","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962062","url":null,"abstract":"As the advance in semiconductor technologies, transient faults caused by particle strike in combinational logic, so-called SETs, have become a matter of concern, and further it is predicted that such faults can span across more than one clock cycle. This paper presents a scheduling algorithm in high-level synthesis of long duration transient fault tolerant datapaths. On the basis of the properties of operational units for error correction and detection in behaviorally tripled module systems, we introduce the concept of forces among operations in unscheduled data-flow graphs, and propose a scheduling algorithm based on well-known force-directed scheduling. Experimental results show that the proposed scheduling algorithm can derive multi-cycle fault tolerant datapaths with small hardware resources compared with simply-tripled datapaths.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133167051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962101
Wisam Aljubouri, Ahish Mysore Somashekar, T. Haniotakis, S. Tragoudas
A novel technique based on the current profile of path segments is presented. Certain current profiles can provide significant insights into the delay characteristics of the segments. They can assist in post-silicon diagnosis for delay defects and also determine shifts in the values of process parameters along the segments. A method to excite such current profiles is presented. Experimental evaluation on benchmark circuits shows the effectiveness of the approach.
{"title":"Diagnosis of segment delay defects with current sensing","authors":"Wisam Aljubouri, Ahish Mysore Somashekar, T. Haniotakis, S. Tragoudas","doi":"10.1109/DFT.2014.6962101","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962101","url":null,"abstract":"A novel technique based on the current profile of path segments is presented. Certain current profiles can provide significant insights into the delay characteristics of the segments. They can assist in post-silicon diagnosis for delay defects and also determine shifts in the values of process parameters along the segments. A method to excite such current profiles is presented. Experimental evaluation on benchmark circuits shows the effectiveness of the approach.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133496486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962069
Angelo Bacchini, M. Rovatti, G. Furano, M. Ottavi
Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell's ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults.
{"title":"Characterization of data retention faults in DRAM devices","authors":"Angelo Bacchini, M. Rovatti, G. Furano, M. Ottavi","doi":"10.1109/DFT.2014.6962069","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962069","url":null,"abstract":"Dynamic random access memory (DRAM) is the most widely used type of memory in the consumer market today, and it is still widely used for mass memories for space application. Even though accurate tests are performed by vendors to ensure high reliability, DRAM errors continue to be a common source of failures in the field. Recent large-scale studies reported how most of the errors experienced by DRAM subsystem are due to faults repeating on the same memory address but occurring only under specific condition. As these failures could be related to the memory cell's ability to retain its stored charge, an empirical characterization of DRAM data retention time was performed within this study. Retention time information was collected from SDRAM devices from two different vendors to evaluate the impact of four different factors (temperature, data background, previous charge level and variable retention time) on DRAM cells retention time. Gathered results can be useful in defining enhanced test procedures for the early detection of data retention faults.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132889460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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