Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962089
S. Keshavarz, Amirreza Nekooei, Z. Navabi
Technology scaling, increasing transistor density, and design complexity poses new challenges in testing of digital systems. IJTAG is a new proposed standard to access embedded instruments in a chip. However, with growing complexity of embedded chips, shifting data serially might result in high test application time. In this paper, a preemptive parallel test scheduling method for IJTAG environment is introduced to reduce test application time while considering maximum power limitation. Furthermore, an architecture is proposed to support fully reconfigurable multi-bit IJTAG architecture that could be changed at runtime. Experimental results show that applying the proposed method for the framework results in test application time reduction in comparison with other existing methods.
{"title":"Preemptive multi-bit IJTAG testing with reconfigurable infrastructure","authors":"S. Keshavarz, Amirreza Nekooei, Z. Navabi","doi":"10.1109/DFT.2014.6962089","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962089","url":null,"abstract":"Technology scaling, increasing transistor density, and design complexity poses new challenges in testing of digital systems. IJTAG is a new proposed standard to access embedded instruments in a chip. However, with growing complexity of embedded chips, shifting data serially might result in high test application time. In this paper, a preemptive parallel test scheduling method for IJTAG environment is introduced to reduce test application time while considering maximum power limitation. Furthermore, an architecture is proposed to support fully reconfigurable multi-bit IJTAG architecture that could be changed at runtime. Experimental results show that applying the proposed method for the framework results in test application time reduction in comparison with other existing methods.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125252008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-24DOI: 10.1109/DFT.2014.6962077
Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, M. Onabajo, Yong-Bin Kim
A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. To compensate the low gain of an envelope detector and to enhance reliability of spectral analysis, an RF amplifier is designed between the LNA and the envelope detector. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total time required for calibration is 485μs including delays of 1.2μs to allow settling of the LNA output after capacitor array changes for tuning. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed with the same condition at transient simulations, where the results are well matched with the optimum IM3 component values calculated at the output node of LNA. The digital blocks were implemented using a standard 0.13μm CMOS technology.
{"title":"A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA","authors":"Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, M. Onabajo, Yong-Bin Kim","doi":"10.1109/DFT.2014.6962077","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962077","url":null,"abstract":"A digital built-in calibration (BIC) system with a power and area optimized on-chip fast Fourier transform (FFT) engine is presented to automatically adjust the linearity of a tunable RF low-noise amplifier (LNA) operating at 2.4GHz. An envelope detection circuit is used to extract the linearity characteristics at low frequencies, enabling the sampling and digital signal processing at low rates. To compensate the low gain of an envelope detector and to enhance reliability of spectral analysis, an RF amplifier is designed between the LNA and the envelope detector. The output of the envelope detector is digitized before the spectrum calculation with the integrated FFT for estimation of the third-order intermodulation (IM3) distortion specification of the LNA. The digitally-assisted closed-loop calibration scheme is demonstrated with simulations using a two-tone test with 1MHz tone spacing, a 512-point FFT engine, a 10-bit analog-to-digital converter model, and digital blocks operating with a 51.2MHz clock frequency. The total time required for calibration is 485μs including delays of 1.2μs to allow settling of the LNA output after capacitor array changes for tuning. In order to validate the proposed BIC technique with device mismatch effects, Monte Carlo simulations are performed with the same condition at transient simulations, where the results are well matched with the optimum IM3 component values calculated at the output node of LNA. The digital blocks were implemented using a standard 0.13μm CMOS technology.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116817159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962105
Senwen Kan, Jennifer Dworak
Over the past several years, there has been growing concern regarding the possibility that Hardware Trojan Horse circuits may be present in 3rd party IP. In this paper, we focus specifically on 3rd party IP related to Static Random-Access Memories (SRAMs), and we demonstrate that some Trojans in production-worthy SRAM circuits can easily evade standard verification techniques. We then describe a novel Trojan detection mechanism based on X-propagation during functional simulation of verification vectors. Our experiments from a silicon-worthy verification environment illustrate that our techniques can be significantly more effective at Trojan detection than standard SRAM verification practices.
{"title":"Triggering Trojans in SRAM circuits with X-propagation","authors":"Senwen Kan, Jennifer Dworak","doi":"10.1109/DFT.2014.6962105","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962105","url":null,"abstract":"Over the past several years, there has been growing concern regarding the possibility that Hardware Trojan Horse circuits may be present in 3rd party IP. In this paper, we focus specifically on 3rd party IP related to Static Random-Access Memories (SRAMs), and we demonstrate that some Trojans in production-worthy SRAM circuits can easily evade standard verification techniques. We then describe a novel Trojan detection mechanism based on X-propagation during functional simulation of verification vectors. Our experiments from a silicon-worthy verification environment illustrate that our techniques can be significantly more effective at Trojan detection than standard SRAM verification practices.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121987766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962102
Prashant D. Joshi, S. Hamdioui
Shortest path determination in a class of optimally fault tolerant networks designed using modified line graphs is described here. Appropriate node naming allows the shortest paths to be determined in 0(log n) steps. This is applicable even in the presence of node failures, without loops or backtracking. The stretch of the network is maintained at the theoretically minimum value possible of one.
{"title":"Shortest path reduction in a class of uniform fault tolerant networks","authors":"Prashant D. Joshi, S. Hamdioui","doi":"10.1109/DFT.2014.6962102","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962102","url":null,"abstract":"Shortest path determination in a class of optimally fault tolerant networks designed using modified line graphs is described here. Appropriate node naming allows the shortest paths to be determined in 0(log n) steps. This is applicable even in the presence of node failures, without loops or backtracking. The stretch of the network is maintained at the theoretically minimum value possible of one.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123766217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962072
Mario Schölzel, T. Koal, H. Vierhaus
Diagnostic self-test in-the-field for processors becomes mandatory for reconfigurable fault tolerant processor-based systems. Software-based self-test techniques are well suited for providing a pass/fail test in-the-field. However, a diagnostic result for dynamically scheduled processors is usually not obtained by these tests, because the software has no control about the used components of the processor during the execution of the test program. This paper provides a concept for a simple hardware extension of a dynamically scheduled processor, such that the test program gets control about the resource usage. With this technique, for the first time, it becomes feasible to perform a diagnostic software-based self-test for dynamically scheduled processors that is able to distinguish between faults in various components of the processor. In particular, the instruction queue, reservation stations, functional units, and reorder buffer are taken into account. Thereby, the hardware overhead for self-test and reconfiguration is less than 6%.
{"title":"Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults","authors":"Mario Schölzel, T. Koal, H. Vierhaus","doi":"10.1109/DFT.2014.6962072","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962072","url":null,"abstract":"Diagnostic self-test in-the-field for processors becomes mandatory for reconfigurable fault tolerant processor-based systems. Software-based self-test techniques are well suited for providing a pass/fail test in-the-field. However, a diagnostic result for dynamically scheduled processors is usually not obtained by these tests, because the software has no control about the used components of the processor during the execution of the test program. This paper provides a concept for a simple hardware extension of a dynamically scheduled processor, such that the test program gets control about the resource usage. With this technique, for the first time, it becomes feasible to perform a diagnostic software-based self-test for dynamically scheduled processors that is able to distinguish between faults in various components of the processor. In particular, the instruction queue, reservation stations, functional units, and reorder buffer are taken into account. Thereby, the hardware overhead for self-test and reconfiguration is less than 6%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123285316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962063
M. Omaña, Daniele Rossi, Edda Beniamino, C. Metra, C. Tirumurti, R. Galivanche
The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.
{"title":"Power droop reduction during Launch-On-Shift scan-based logic BIST","authors":"M. Omaña, Daniele Rossi, Edda Beniamino, C. Metra, C. Tirumurti, R. Galivanche","doi":"10.1109/DFT.2014.6962063","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962063","url":null,"abstract":"The generation of significant power droop (PD) during at-speed test performed by Logic BIST is a concern for modern ICs. In fact, during test, PD may significantly increase the delay of signals of the circuit under test (CUT), an effect that may be erroneously recognized as presence of delay faults, with consequent erroneous generation of test fails, and increase in yield loss. In this paper, we propose a novel approach to reduce PD during at-speed test with scan-based Logic BIST using the Launch-On-Shift scheme. Our approach increases the correlation between adjacent bits of the scan chains with respect to conventional scan-based LBIST. This way, when the test vectors are applied, the activity factor (AF) of the scan chains is reduced by approximately the 50% with respect to conventional scan-based LBIST, with no drawbacks on test length and fault coverage, and at the cost of very limited area overhead. We also show that compared to two recent alternate solutions, our approach features a comparable AF in the scan chains during the application of test vectors, while it requires a significantly lower test time or area overhead.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130284813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962065
D. Sorrenti, D. Cozzi, S. Korf, Luca Cassano, J. Hagemeyer, Mario Porrmann, C. Bernardeschi
Reconfigurable systems are increasingly employed in many application fields, including aerospace. The long term exposure to radiation of space electronics can cause permanent faults, that may lead to the failure of the mission. In this paper we present a novel technique for on-line on-demand testing of permanent faults in the routing structure of SRAM-based FPGAs, that are employed in reconfigurable systems. The basic idea is to place testing circuits on the resources of the FPGA which are unused at the moment to test them before using those resources when a functional module of the reconfigurable system has to be placed. The proposed technique has been implemented and the achieved fault coverage has been assessed on a real-world reconfigurable system. This experiment demonstrated that all the faults in the routing resources under test can be detected.
{"title":"Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems","authors":"D. Sorrenti, D. Cozzi, S. Korf, Luca Cassano, J. Hagemeyer, Mario Porrmann, C. Bernardeschi","doi":"10.1109/DFT.2014.6962065","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962065","url":null,"abstract":"Reconfigurable systems are increasingly employed in many application fields, including aerospace. The long term exposure to radiation of space electronics can cause permanent faults, that may lead to the failure of the mission. In this paper we present a novel technique for on-line on-demand testing of permanent faults in the routing structure of SRAM-based FPGAs, that are employed in reconfigurable systems. The basic idea is to place testing circuits on the resources of the FPGA which are unused at the moment to test them before using those resources when a functional module of the reconfigurable system has to be placed. The proposed technique has been implemented and the achieved fault coverage has been assessed on a real-world reconfigurable system. This experiment demonstrated that all the faults in the routing resources under test can be detected.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962090
P. Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, E. Sánchez, M. Reorda, S. D. Luca, Renato Meregalli, A. Sansonetti
The paper is dealing with the in-field test of the decode unit of RISC processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the netlist), but is based on the Instruction Set of the processor. The proposed method is evaluated on an industrial SoC device, which includes a PowerPC derived processor. Results demonstrate the efficiency and effectiveness of the strategy; the proposed solution reaches over 90% of stuck-at fault coverage while an instruction coverage based approach does not overcome 70%.
{"title":"On the in-field functional testing of decode units in pipelined RISC processors","authors":"P. Bernardi, R. Cantoro, Lyl M. Ciganda Brasca, E. Sánchez, M. Reorda, S. D. Luca, Renato Meregalli, A. Sansonetti","doi":"10.1109/DFT.2014.6962090","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962090","url":null,"abstract":"The paper is dealing with the in-field test of the decode unit of RISC processors through functional test programs following the SBST approach. The paper details a strategy based on instruction classification and manipulation, and signatures collection. The method does not require the knowledge of detailed implementation information (e.g., the netlist), but is based on the Instruction Set of the processor. The proposed method is evaluated on an industrial SoC device, which includes a PowerPC derived processor. Results demonstrate the efficiency and effectiveness of the strategy; the proposed solution reaches over 90% of stuck-at fault coverage while an instruction coverage based approach does not overcome 70%.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-01DOI: 10.1109/DFT.2014.6962098
J. Backer, D. Hély, R. Karri
Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn't require modifications to the SoC.
{"title":"Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip","authors":"J. Backer, D. Hély, R. Karri","doi":"10.1109/DFT.2014.6962098","DOIUrl":"https://doi.org/10.1109/DFT.2014.6962098","url":null,"abstract":"Systems-on-chip (SoCs) are vulnerable to attacks by malicious software and hardware trojans. This work explores if the Design for Test (DfT) infrastructure in SoCs can tackle these security threats with minimum hardware overhead. We show that the observability and plug-and-play features of the IEEE 1500 DfT can be used for scalable security monitoring in SoCs. Existing SoC security countermeasures can reuse the DfT-based security architecture to detect software and hardware attacks. The proposed DfT reuse imposes negligible hardware and performance overheads and doesn't require modifications to the SoC.","PeriodicalId":414665,"journal":{"name":"2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126107142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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