Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512399
M. Allen, W. Lewchuk
With the PowerPC 620 microprocessor, we introduce a new bus optimized for server-class systems requiring significant multiprocessing capability. The 620 bus supports the 64-bit PowerPC Architecture specification with a 40-bit physical address bus and a separate 128-bit data bus. The address snoop response is pipelined with the address bus, providing an address transfer rate of up to 33M Addresses/sec at 66 MHz. Completion of address bus operations can be reordered with respect to operation initiation. The address and data buses are explicitly tagged allowing data transfers to be reordered with respect to the addresses. The data bus can transfer up to 1.0 GB/sec at 66 MHz. The bus protocol presented supports the snoop-based MESI cache coherency protocol and direct cache-to-cache data transfers.
{"title":"A pipelined, weakly ordered bus for multiprocessing systems","authors":"M. Allen, W. Lewchuk","doi":"10.1109/CMPCON.1995.512399","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512399","url":null,"abstract":"With the PowerPC 620 microprocessor, we introduce a new bus optimized for server-class systems requiring significant multiprocessing capability. The 620 bus supports the 64-bit PowerPC Architecture specification with a 40-bit physical address bus and a separate 128-bit data bus. The address snoop response is pipelined with the address bus, providing an address transfer rate of up to 33M Addresses/sec at 66 MHz. Completion of address bus operations can be reordered with respect to operation initiation. The address and data buses are explicitly tagged allowing data transfers to be reordered with respect to the addresses. The data bus can transfer up to 1.0 GB/sec at 66 MHz. The bus protocol presented supports the snoop-based MESI cache coherency protocol and direct cache-to-cache data transfers.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132100661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512371
J. O. Nicholson
The IBM RISC System/6000 Symmetric Multiprocessor is a new addition to IBM's successful line of RISC-based commercial servers. It utilizes balanced system design principles and introduces new levels of function and scalability. This paper will focus on design issues and technical attributes pertinent to achieving these goals.
IBM RISC System/6000对称多处理器是IBM基于RISC的商业服务器成功产品线的新成员。它采用平衡的系统设计原则，并引入了新的功能和可扩展性。本文将关注与实现这些目标相关的设计问题和技术属性。
{"title":"The RISC system/6000 SMP system","authors":"J. O. Nicholson","doi":"10.1109/CMPCON.1995.512371","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512371","url":null,"abstract":"The IBM RISC System/6000 Symmetric Multiprocessor is a new addition to IBM's successful line of RISC-based commercial servers. It utilizes balanced system design principles and introduces new levels of function and scalability. This paper will focus on design issues and technical attributes pertinent to achieving these goals.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512424
Chang-Guo Zhou, Leslie Kohn, D. Rice, Ihtisham Kabir, Aman Jabbi, Xiao-Ping Hu
The UltraSPARC microprocessor is equipped with a rich "visual instruction set" (VIS) which can perform ALU and other operations on several pixels in parallel. Significant performance gains are possible in the areas of video compression and decompression, as well as other areas of image processing. In this paper, we present a computational complexity analysis of MPEG video decompression, and derive a quantitative performance bound for software MPEG decoders. Based on this estimate, we show that by combining VIS and a high superscalar instruction rate, UltraSPARC is capable of decoding MPEG digital video at 720/spl times/480/spl times/30 resolution entirely in software. A coding example for the YUV to RGB colorspace conversion is also presented.
{"title":"MPEG video decoding with the UltraSPARC visual instruction set","authors":"Chang-Guo Zhou, Leslie Kohn, D. Rice, Ihtisham Kabir, Aman Jabbi, Xiao-Ping Hu","doi":"10.1109/CMPCON.1995.512424","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512424","url":null,"abstract":"The UltraSPARC microprocessor is equipped with a rich \"visual instruction set\" (VIS) which can perform ALU and other operations on several pixels in parallel. Significant performance gains are possible in the areas of video compression and decompression, as well as other areas of image processing. In this paper, we present a computational complexity analysis of MPEG video decompression, and derive a quantitative performance bound for software MPEG decoders. Based on this estimate, we show that by combining VIS and a high superscalar instruction rate, UltraSPARC is capable of decoding MPEG digital video at 720/spl times/480/spl times/30 resolution entirely in software. A coding example for the YUV to RGB colorspace conversion is also presented.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512426
D. Long, P. Mantey, C. Wittenbrink, Theodore R. Haining, B. Montague
The Real-Time Environmental Information Network and Analysis System (REINAS) is a distributed system supporting the conduct of regional environmental science research at the desk top. Continuous real-time data acquired from dispersed sensors is stored in a logically integrated but physically distributed data base. An integrated problem-solving environment is under development which supports visualization and modeling. REINAS is intended to provide insight into historical, current, and predicted oceanographic and meteorological conditions. REINAS permits both collaborative and single-user scientific work in a distributed environment.
{"title":"REINAS: the Real-time Environmental Information Network and Analysis System","authors":"D. Long, P. Mantey, C. Wittenbrink, Theodore R. Haining, B. Montague","doi":"10.1109/CMPCON.1995.512426","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512426","url":null,"abstract":"The Real-Time Environmental Information Network and Analysis System (REINAS) is a distributed system supporting the conduct of regional environmental science research at the desk top. Continuous real-time data acquired from dispersed sensors is stored in a logically integrated but physically distributed data base. An integrated problem-solving environment is under development which supports visualization and modeling. REINAS is intended to provide insight into historical, current, and predicted oceanographic and meteorological conditions. REINAS permits both collaborative and single-user scientific work in a distributed environment.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133874432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512422
S. Mehta, S. Ahmed, S. Al-Ashari, Dennis Chen, D. Chen, S. Cokmez, R. Eltejaein, P. Fu, J. Gee, T. Granvold, A. Iyer, A. K. Lin, G. Maturana, D. McConn, H. Mohammed, Jamshid Mostoufi, A. Moudgal, S. Nori, G. Peterson, M. Splain, T. Yu
The overall verification approach used in the design and development of the full custom 64 bit UltraSPARC microprocessor is described. A balanced hierarchical approach is critical in validating a design with this level of complexity. The tools, developed internally and externally, which aided the verification effort are also described. The environment is flexible enough to support various revisions of major tools. The method developed could easily be applied to derivative and next generation microprocessors.
{"title":"Verification of the UltraSPARC microprocessor","authors":"S. Mehta, S. Ahmed, S. Al-Ashari, Dennis Chen, D. Chen, S. Cokmez, R. Eltejaein, P. Fu, J. Gee, T. Granvold, A. Iyer, A. K. Lin, G. Maturana, D. McConn, H. Mohammed, Jamshid Mostoufi, A. Moudgal, S. Nori, G. Peterson, M. Splain, T. Yu","doi":"10.1109/CMPCON.1995.512422","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512422","url":null,"abstract":"The overall verification approach used in the design and development of the full custom 64 bit UltraSPARC microprocessor is described. A balanced hierarchical approach is critical in validating a design with this level of complexity. The tools, developed internally and externally, which aided the verification effort are also described. The environment is flexible enough to support various revisions of major tools. The method developed could easily be applied to derivative and next generation microprocessors.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134461162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512385
A. C. Barkans
A method to produce true color images from a typical low cost 8-bit frame buffer is discussed. This method, called Color Recovery, is a two part process. The first part of the process is to sample true color data generated by an application in order to reduce 24-bit color to 8 bits for storage in the frame buffer. The second part of the process is to use specialized digital signal processing logic to reconstruct the true color image from the 8-bit frame buffer. This part of the process is preformed as the data is being scanned from the frame buffer to the display.
{"title":"Color recovery: millions of colors from an 8-bit graphics device","authors":"A. C. Barkans","doi":"10.1109/CMPCON.1995.512385","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512385","url":null,"abstract":"A method to produce true color images from a typical low cost 8-bit frame buffer is discussed. This method, called Color Recovery, is a two part process. The first part of the process is to sample true color data generated by an application in order to reduce 24-bit color to 8 bits for storage in the frame buffer. The second part of the process is to use specialized digital signal processing logic to reconstruct the true color image from the 8-bit frame buffer. This part of the process is preformed as the data is being scanned from the frame buffer to the display.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132698525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512386
Lee Colby
The Digital settop converters that are on the drawing boards now will be able to support near video on demand (NVOD), electronic program guide and simple interactivity. Most of the return path information will be information relating to services received and billing information. The first settops will be closely followed by settop converters that support full video on demand with more capable graphics and interactivity. They are characterized by the ability to receive both analog and digital television signals. This paper discusses one implementation of a CATV settop converter's digital RF modems and how a PC modem might differ from the CATV modem.
{"title":"Overview of interactive TV from the viewpoint of the cable TV settop converter's RF modem","authors":"Lee Colby","doi":"10.1109/CMPCON.1995.512386","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512386","url":null,"abstract":"The Digital settop converters that are on the drawing boards now will be able to support near video on demand (NVOD), electronic program guide and simple interactivity. Most of the return path information will be information relating to services received and billing information. The first settops will be closely followed by settop converters that support full video on demand with more capable graphics and interactivity. They are characterized by the ability to receive both analog and digital television signals. This paper discusses one implementation of a CATV settop converter's digital RF modems and how a PC modem might differ from the CATV modem.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512393
W. Wilcke
This paper gives a high-level, architectural overview of a line of 64-bit SPARC based workstations and servers designed by HaL Computer Systems. It discusses target applications, highlights of the SPARC V9 instruction set, HaL-specific instructions and a highly scalable multi-processor system architecture. The paper concludes with a summary of 64-bit software compatibility issues, system performance and reliability/availability/serviceability features.
{"title":"Architectural overview of HaL systems","authors":"W. Wilcke","doi":"10.1109/CMPCON.1995.512393","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512393","url":null,"abstract":"This paper gives a high-level, architectural overview of a line of 64-bit SPARC based workstations and servers designed by HaL Computer Systems. It discusses target applications, highlights of the SPARC V9 instruction set, HaL-specific instructions and a highly scalable multi-processor system architecture. The paper concludes with a summary of 64-bit software compatibility issues, system performance and reliability/availability/serviceability features.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129814679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512373
B. Olszewski, Jean-Jacques Guillemaud
The first PowerPC-based SMP jointly developed by IBM and Croup Bull, had aggressive performance goals for its intended market of commercial applications. This paper describes the hardware and software design processes used in the product development, as well as performance results obtained on the first-generation PowerPC 601-based hardware.
{"title":"The performance and performance methodology for a PowerPC SMP system","authors":"B. Olszewski, Jean-Jacques Guillemaud","doi":"10.1109/CMPCON.1995.512373","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512373","url":null,"abstract":"The first PowerPC-based SMP jointly developed by IBM and Croup Bull, had aggressive performance goals for its intended market of commercial applications. This paper describes the hardware and software design processes used in the product development, as well as performance results obtained on the first-generation PowerPC 601-based hardware.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125396891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512374
Doug Hunt
The PA-8000 is Hewlett-Packard's first CPU to implement the new 64-bit PA2.0 architecture. It combines a high clock frequency with a number of advanced microarchitectural features to deliver industry-leading performance on commercial and technical applications while maintaining full compatibility with all previous PA-RISC binaries. Among these advanced features are a fifty-six entry instruction reorder buffer to support out-of-order execution, a branch target address cache, branch history table, support for multiple outstanding cache misses and dual integer load/store, floating point multiply/accumulate, and divide/square root units which allow execution of four instructions per cycle. Together these features will enable the PA-8000 to sustain superscalar operation on a wide variety of workloads.
{"title":"Advanced performance features of the 64-bit PA-8000","authors":"Doug Hunt","doi":"10.1109/CMPCON.1995.512374","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512374","url":null,"abstract":"The PA-8000 is Hewlett-Packard's first CPU to implement the new 64-bit PA2.0 architecture. It combines a high clock frequency with a number of advanced microarchitectural features to deliver industry-leading performance on commercial and technical applications while maintaining full compatibility with all previous PA-RISC binaries. Among these advanced features are a fifty-six entry instruction reorder buffer to support out-of-order execution, a branch target address cache, branch history table, support for multiple outstanding cache misses and dual integer load/store, floating point multiply/accumulate, and divide/square root units which allow execution of four instructions per cycle. Together these features will enable the PA-8000 to sustain superscalar operation on a wide variety of workloads.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128560388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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