Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512381
My T. Le, Frederick L. Burghard, S. Seshan, J. Rabaey
This paper provides an overview of InfoNet, the networking infrastructure for the InfoPad mobile computing system. First, the goals and architecture of InfoNet is defined. Next, the current implementation, performance measurements, and proxy connections are discussed. Finally, we present the future directions for InfoNet.
{"title":"InfoNet: The networking infrastructure of InfoPad","authors":"My T. Le, Frederick L. Burghard, S. Seshan, J. Rabaey","doi":"10.1109/CMPCON.1995.512381","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512381","url":null,"abstract":"This paper provides an overview of InfoNet, the networking infrastructure for the InfoPad mobile computing system. First, the goals and architecture of InfoNet is defined. Next, the current implementation, performance measurements, and proxy connections are discussed. Finally, we present the future directions for InfoNet.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123295399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512358
M. Sirbu, J. D. Tygar
NetBill is a business model, set of protocols, and software implementation for supporting commerce in information goods and other network delivered services. It has very low transaction costs for micropayments (around 1 cent for a 10cent item), protects the privacy of the transaction, and is highly scalable. Of special interest is our new certified delivery mechanism which delivers information goods if and only if the customer has payed for them. This paper discusses the design of the NetBill protocol and our World Wide Web (WWW) prototype implementation.
{"title":"NetBill: An Internet commerce system optimized for network delivered services","authors":"M. Sirbu, J. D. Tygar","doi":"10.1109/CMPCON.1995.512358","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512358","url":null,"abstract":"NetBill is a business model, set of protocols, and software implementation for supporting commerce in information goods and other network delivered services. It has very low transaction costs for micropayments (around 1 cent for a 10cent item), protects the privacy of the transaction, and is highly scalable. Of special interest is our new certified delivery mechanism which delivers information goods if and only if the customer has payed for them. This paper discusses the design of the NetBill protocol and our World Wide Web (WWW) prototype implementation.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512391
V. Nirkhe, M. Baugher
Existing media players, the applications that allow access to stored multimedia data, have been designed for standalone use. Consequently, they do not provide quality of service (QoS) support needed for access to remote data. In this paper, we describe QoS architecture provided in OS/2 multimedia extensions. This architecture defines layered QoS definitions consisting of user-specific, data-specific and network-specific categories. Applications use user-specific QoS parameters, which are translated into network-specific parameters by the system. Such a scheme provides portability allowing access to data stored on different types of file servers residing on a variety of networks without the application being aware of the network QoS mechanisms.
{"title":"Quality of service support for networked media players","authors":"V. Nirkhe, M. Baugher","doi":"10.1109/CMPCON.1995.512391","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512391","url":null,"abstract":"Existing media players, the applications that allow access to stored multimedia data, have been designed for standalone use. Consequently, they do not provide quality of service (QoS) support needed for access to remote data. In this paper, we describe QoS architecture provided in OS/2 multimedia extensions. This architecture defines layered QoS definitions consisting of user-specific, data-specific and network-specific categories. Applications use user-specific QoS parameters, which are translated into network-specific parameters by the system. Such a scheme provides portability allowing access to data stored on different types of file servers residing on a variety of networks without the application being aware of the network QoS mechanisms.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131681519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512416
Garth A. Gibson, Daniel Stodolsky, Fay W. Chang, William V. Courtright, C. Demetriou, E. Ginting, M. Holland, Qingming Ma, LeAnn Neal, R. H. Patterson, Jiawen Su, Rachad Youssef, J. Zelenka
To meet the bandwidth needs of modern computer systems, parallel storage systems are evolving beyond RAID levels 1 through 5. The parallel Data Lab at Carnegie Mellon University has constructed three Scotch parallel storage testbeds to explore and evaluate five directions in RAID evolution: first, the development of new RAID architectures to reduce the cost/performance penalty of maintaining redundant data; second, an extensible software framework for rapid prototyping of new architectures; third, mechanisms to reduce the complexity of and automate error-handling in RAID subsystems; fourth, a file system extension that allows serial programs to exploit parallel storage; and lastly, a parallel file system that extends the RAID advantages to distributed parallel computing environments. This paper describes these five RAID evolutions and the testbeds in which they are being implemented and evaluated.
为了满足现代计算机系统的带宽需求，并行存储系统正在从RAID 1级发展到RAID 5级。卡内基梅隆大学(Carnegie Mellon University)的并行数据实验室(parallel Data Lab)构建了三个Scotch并行存储测试平台，以探索和评估RAID演进的五个方向:第一，开发新的RAID架构，以减少维护冗余数据的成本/性能损失;第二，一个可扩展的软件框架，用于新架构的快速原型设计;第三，降低RAID子系统的复杂性和自动化错误处理的机制;第四，允许串行程序利用并行存储的文件系统扩展;最后，一个将RAID优势扩展到分布式并行计算环境的并行文件系统。本文描述了这五种RAID演进，以及它们被实现和评估的测试平台。
{"title":"The Scotch parallel storage systems","authors":"Garth A. Gibson, Daniel Stodolsky, Fay W. Chang, William V. Courtright, C. Demetriou, E. Ginting, M. Holland, Qingming Ma, LeAnn Neal, R. H. Patterson, Jiawen Su, Rachad Youssef, J. Zelenka","doi":"10.1109/CMPCON.1995.512416","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512416","url":null,"abstract":"To meet the bandwidth needs of modern computer systems, parallel storage systems are evolving beyond RAID levels 1 through 5. The parallel Data Lab at Carnegie Mellon University has constructed three Scotch parallel storage testbeds to explore and evaluate five directions in RAID evolution: first, the development of new RAID architectures to reduce the cost/performance penalty of maintaining redundant data; second, an extensible software framework for rapid prototyping of new architectures; third, mechanisms to reduce the complexity of and automate error-handling in RAID subsystems; fourth, a file system extension that allows serial programs to exploit parallel storage; and lastly, a parallel file system that extends the RAID advantages to distributed parallel computing environments. This paper describes these five RAID evolutions and the testbeds in which they are being implemented and evaluated.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127152553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512420
J. Gast
While the mechanisms of hierarchical storage management may be well understood, the metrics used to measure the effectiveness of HSM and the variables used to justify purchasing an HSM system are not well defined. Moreover, there are some potholes on the road to configuring an efficient HSM system. This paper suggests a set of steps from justifying the expense to making sure HSM integrates well with the other storage management functions already in place.
{"title":"Metrics to use on the road to HSM","authors":"J. Gast","doi":"10.1109/CMPCON.1995.512420","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512420","url":null,"abstract":"While the mechanisms of hierarchical storage management may be well understood, the metrics used to measure the effectiveness of HSM and the variables used to justify purchasing an HSM system are not well defined. Moreover, there are some potholes on the road to configuring an efficient HSM system. This paper suggests a set of steps from justifying the expense to making sure HSM integrates well with the other storage management functions already in place.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127181287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512415
Edward K. F. Lee
The ideal storage system is always available, is incrementally expandable, scales in performance as new components are added and requires no management. Existing storage systems are far from this ideal. The recent introduction of low-cost, scalable, high-performance networks allows us to re-examine the way we build storage systems and to investigate storage architectures that bring us closer to the ideal storage system. This document examines some of the issues and ideas in building such storage systems and describes our first scalable storage prototype.
{"title":"Highly-available, scalable network storage","authors":"Edward K. F. Lee","doi":"10.1109/CMPCON.1995.512415","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512415","url":null,"abstract":"The ideal storage system is always available, is incrementally expandable, scales in performance as new components are added and requires no management. Existing storage systems are far from this ideal. The recent introduction of low-cost, scalable, high-performance networks allows us to re-examine the way we build storage systems and to investigate storage architectures that bring us closer to the ideal storage system. This document examines some of the issues and ideas in building such storage systems and describes our first scalable storage prototype.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125352268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512368
P. Bannon, J. Keller
The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.
{"title":"Internal architecture of Alpha 21164 microprocessor","authors":"P. Bannon, J. Keller","doi":"10.1109/CMPCON.1995.512368","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512368","url":null,"abstract":"The internal architecture of a 1200 MIPS/600 MFLOPS (peak) high-performance CMOS ALPHA microprocessor chip is described. This second-generation implementation is the world's fastest microprocessor. It contains a quad-issue superscalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit combine to form a high-perfomance memory sub-system with MP coherent writeback caches.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116968024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512401
J. K. Yuan, M. Taborn, David Lee, Albert Tsay
PowerPC 620 microprocessor was developed with distributed computing in mind. Several design techniques found in distributed applications have been employed in designing the processor core as well as the processor-system interface. Superscalar and speculative execution are two key implementation factors that push the processor performance to a new height. The processor is a 64-bit implementation of the PowerPC Architecture specification and is designed for high-end workstation and server markers. Application of PowerPC 620 microprocessor in a multimedia workstation and a multimedia server will be discussed in details.
{"title":"The PowerPC 620 microprocessor in distributed computing","authors":"J. K. Yuan, M. Taborn, David Lee, Albert Tsay","doi":"10.1109/CMPCON.1995.512401","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512401","url":null,"abstract":"PowerPC 620 microprocessor was developed with distributed computing in mind. Several design techniques found in distributed applications have been employed in designing the processor core as well as the processor-system interface. Superscalar and speculative execution are two key implementation factors that push the processor performance to a new height. The processor is a 64-bit implementation of the PowerPC Architecture specification and is designed for high-end workstation and server markers. Application of PowerPC 620 microprocessor in a multimedia workstation and a multimedia server will be discussed in details.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125249976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512400
C. Peng, T. A. Petersen, Ron Clark
This paper details the 64-bit PowerPC Architecture specification. It compares and contrasts the 32-bit subset specification against the full 64-bit specification. Architecture, application OS, and hardware implications of the 64-bit specifications are all explored in detail. In addition, 32- and 64-bit compatibility and OS migration strategies are described. The PowerPC 620 microprocessor implementation is used as a vehicle when examining the 64-bit features. The 620's MMU is described, and potential performance implications are discussed.
{"title":"The PowerPC Architecture: 64-bit power with 32-bit compatibility","authors":"C. Peng, T. A. Petersen, Ron Clark","doi":"10.1109/CMPCON.1995.512400","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512400","url":null,"abstract":"This paper details the 64-bit PowerPC Architecture specification. It compares and contrasts the 32-bit subset specification against the full 64-bit specification. Architecture, application OS, and hardware implications of the 64-bit specifications are all explored in detail. In addition, 32- and 64-bit compatibility and OS migration strategies are described. The PowerPC 620 microprocessor implementation is used as a vehicle when examining the 64-bit features. The 620's MMU is described, and potential performance implications are discussed.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124102558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-03-05DOI: 10.1109/CMPCON.1995.512406
D. Gustavson, Qiang Li
Clusters, or networks, of workstations (NOW) have proven their value for certain classes of applications, those that can be efficiently parallelized with coarse granularity requiring relatively little intertask communication. However clusters of workstations have been ineffective for those classes of applications that require fine-grained parallelization or too much intertask communication, because of the high overhead and poor performance of present communication mechanisms. A new international standard reduces this cost by several orders of magnitude compared to present networks or proposed future networks/channels like FibreChannel or ATM. This new technology implements a "Local-Area Multiprocessor" with very high performance message passing and distributed shared memory.
{"title":"Local-area multiprocessor: surpassing clusters","authors":"D. Gustavson, Qiang Li","doi":"10.1109/CMPCON.1995.512406","DOIUrl":"https://doi.org/10.1109/CMPCON.1995.512406","url":null,"abstract":"Clusters, or networks, of workstations (NOW) have proven their value for certain classes of applications, those that can be efficiently parallelized with coarse granularity requiring relatively little intertask communication. However clusters of workstations have been ineffective for those classes of applications that require fine-grained parallelization or too much intertask communication, because of the high overhead and poor performance of present communication mechanisms. A new international standard reduces this cost by several orders of magnitude compared to present networks or proposed future networks/channels like FibreChannel or ATM. This new technology implements a \"Local-Area Multiprocessor\" with very high performance message passing and distributed shared memory.","PeriodicalId":415918,"journal":{"name":"Digest of Papers. COMPCON'95. Technologies for the Information Superhighway","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129248145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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