Pub Date : 1900-01-01DOI: 10.1109/ICCVIA.2015.7351907
Wang-Cheol Song
As interest on the Smart Grid technology has recently increase, research and development of the electric vehicle(EV) as well as studies on the renewable energy, distributed generation and energy storage have been actively conducted. The Electric Vehicle (EV) is an important component in the smart grids, playing a role of the electrical storage component with high capacity. It is an entity to be able to buy and sell the electricity in the grid, but it cannot directly join the electricity market because its capacity is not sufficiently large to make deals in the market. The aggregator buys and sells electricity on the behalf of EVs and negotiates electricity prices in the market. We propose Aggregator operations with an authentication procedure to discriminate an individual user and how an EV working together with the aggregator when charging the EVs is shown.
{"title":"Aggregator operations considering authentication for electrical charging of EVs","authors":"Wang-Cheol Song","doi":"10.1109/ICCVIA.2015.7351907","DOIUrl":"https://doi.org/10.1109/ICCVIA.2015.7351907","url":null,"abstract":"As interest on the Smart Grid technology has recently increase, research and development of the electric vehicle(EV) as well as studies on the renewable energy, distributed generation and energy storage have been actively conducted. The Electric Vehicle (EV) is an important component in the smart grids, playing a role of the electrical storage component with high capacity. It is an entity to be able to buy and sell the electricity in the grid, but it cannot directly join the electricity market because its capacity is not sufficiently large to make deals in the market. The aggregator buys and sells electricity on the behalf of EVs and negotiates electricity prices in the market. We propose Aggregator operations with an authentication procedure to discriminate an individual user and how an EV working together with the aggregator when charging the EVs is shown.","PeriodicalId":419122,"journal":{"name":"International Conference on Computer Vision and Image Analysis Applications","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127416912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ICCVIA.2015.7351893
N. Bahri, N. Belhadj, Med Ali Ben Ayed, N. Masmoudi, T. Grandpierre, M. Akil
In this paper, the newest Texas Instrument's multicore DSP TMS320C6678 is used in order to perform a real-time H264/AVC high definition (HD) embedded video encoder. We exploit the high computing performance offered by this eight-core DSP in order to meet the real-time encoding compliant. To enhance the encoding speed, Frame Level Parallelism (FLP) approach is applied. A master core is reserved to handle data transfers to/from DSP. Multithreading algorithm combined with a ping-pong buffers technique are exploited in order to optimize the standard FLP approach and hide communication overhead. Experimental results show that our enhanced FLP implementation allows achieving real-time HD (1280×720) video encoding by reaching up to 26 f/s (frame/second) as encoding speed. Experiments show also that our parallel implementation, performed on seven C6678 DSP cores running each @ 1 GHz, allows accelerating the encoding run-time by a factor of 6,38 without inducing any quality degradation or bit-rate increase.
{"title":"Real-time H264/AVC high definition video encoder on a multicore DSP TMS320C6678","authors":"N. Bahri, N. Belhadj, Med Ali Ben Ayed, N. Masmoudi, T. Grandpierre, M. Akil","doi":"10.1109/ICCVIA.2015.7351893","DOIUrl":"https://doi.org/10.1109/ICCVIA.2015.7351893","url":null,"abstract":"In this paper, the newest Texas Instrument's multicore DSP TMS320C6678 is used in order to perform a real-time H264/AVC high definition (HD) embedded video encoder. We exploit the high computing performance offered by this eight-core DSP in order to meet the real-time encoding compliant. To enhance the encoding speed, Frame Level Parallelism (FLP) approach is applied. A master core is reserved to handle data transfers to/from DSP. Multithreading algorithm combined with a ping-pong buffers technique are exploited in order to optimize the standard FLP approach and hide communication overhead. Experimental results show that our enhanced FLP implementation allows achieving real-time HD (1280×720) video encoding by reaching up to 26 f/s (frame/second) as encoding speed. Experiments show also that our parallel implementation, performed on seven C6678 DSP cores running each @ 1 GHz, allows accelerating the encoding run-time by a factor of 6,38 without inducing any quality degradation or bit-rate increase.","PeriodicalId":419122,"journal":{"name":"International Conference on Computer Vision and Image Analysis Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134281062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：