Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273534
Yuanchun Li, Yao Guo, Junjun Kong, Xiangqun Chen
As mobile applications (apps) become more and more complex, many apps contain various energy bugs, which may cause energy wastes that might reduce the battery life to as short as several hours. Among them, sensor-related bugs such as sensor data underutilization is one of the most common energy bugs. Instead of trying to detect these energy bugs, this paper proposes a method to fix sensor data underutilization automatically through instrumentation of existing apps. App-specific energy-aware sensing policies can be written to the apps via an automated instrumentation process, which can also be customized by users if needed. The proposed technique is easy to apply as it does not need to modify the operating system or the apps. At the same time, it also works for existing legacy apps, which makes it practical and feasible for a wide-range of mobile apps. Experimental results on popular Android apps show that we are able to achieve significant energy savings through automated instrumentation and rebuilding the targeted apps.
{"title":"Fixing sensor-related energy bugs through automated sensing policy instrumentation","authors":"Yuanchun Li, Yao Guo, Junjun Kong, Xiangqun Chen","doi":"10.1109/ISLPED.2015.7273534","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273534","url":null,"abstract":"As mobile applications (apps) become more and more complex, many apps contain various energy bugs, which may cause energy wastes that might reduce the battery life to as short as several hours. Among them, sensor-related bugs such as sensor data underutilization is one of the most common energy bugs. Instead of trying to detect these energy bugs, this paper proposes a method to fix sensor data underutilization automatically through instrumentation of existing apps. App-specific energy-aware sensing policies can be written to the apps via an automated instrumentation process, which can also be customized by users if needed. The proposed technique is easy to apply as it does not need to modify the operating system or the apps. At the same time, it also works for existing legacy apps, which makes it practical and feasible for a wide-range of mobile apps. Experimental results on popular Android apps show that we are able to achieve significant energy savings through automated instrumentation and rebuilding the targeted apps.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125926472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273524
Chi-Hsuan Lin, Yu-Ming Chang, P. Hsiu, Yuan-Hao Chang
Understanding the implications in smartphone usage and the power breakdown among hardware components has led to various energy-efficient designs for mobile systems. While energy consumption has been extensively explored, one critical dimension is often overlooked - unperceived activities that could steal a significant amount of energy behind users' back potentially. In this paper, we conduct the first exploration of unperceived activities in mobile systems. Specifically, we design a series of experiments to reveal, characterize, and analyze unperceived activities invoked by popular resident applications when an Android smartphone is left unused. We draw possible solutions inspired by the exploration and demonstrate that even an immediate remedy can mitigate energy dissipation to some extent.
{"title":"Energy stealing - an exploration into unperceived activities on mobile systems","authors":"Chi-Hsuan Lin, Yu-Ming Chang, P. Hsiu, Yuan-Hao Chang","doi":"10.1109/ISLPED.2015.7273524","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273524","url":null,"abstract":"Understanding the implications in smartphone usage and the power breakdown among hardware components has led to various energy-efficient designs for mobile systems. While energy consumption has been extensively explored, one critical dimension is often overlooked - unperceived activities that could steal a significant amount of energy behind users' back potentially. In this paper, we conduct the first exploration of unperceived activities in mobile systems. Specifically, we design a series of experiments to reveal, characterize, and analyze unperceived activities invoked by popular resident applications when an Android smartphone is left unused. We draw possible solutions inspired by the exploration and demonstrate that even an immediate remedy can mitigate energy dissipation to some extent.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116410008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273520
Bert Moons, M. Verhelst
A wide variety of existing and emerging applications in recognition, mining and synthesis and machine-to-human interactions tolerate small errors or deviations in their computational results. Digital systems can exploit this error tolerance to increase their energy efficiency, which is crucial in high performance wearable electronics and in emerging low power systems for the internet-of-things. A dynamic energy-accuracy trade-off brings an extra degree of freedom for system level power management. We introduce the concept of Dynamic Voltage Accuracy Scaling and illustrate its analogy to Dynamic Voltage Frequency Scaling. Dynamic Voltage Accuracy Scaling proves to have higher energy gains at most output qualities compared to other approximate computing alternatives. This work further generalizes the Dynamic Voltage Accuracy Scaling concept to pipelined structures and quantifies its energy overhead. Shallow pipelined multipliers with two to four dynamic accuracy modes can be supported with limited (<; 10-20%) overhead, resulting in significant energy savings of up to 90% or more for less than 2% mean error. DVAS is finally applied to a JPEG image processing application, demonstrating large system level gains without noticeable impact to user or application.
{"title":"DVAS: Dynamic Voltage Accuracy Scaling for increased energy-efficiency in approximate computing","authors":"Bert Moons, M. Verhelst","doi":"10.1109/ISLPED.2015.7273520","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273520","url":null,"abstract":"A wide variety of existing and emerging applications in recognition, mining and synthesis and machine-to-human interactions tolerate small errors or deviations in their computational results. Digital systems can exploit this error tolerance to increase their energy efficiency, which is crucial in high performance wearable electronics and in emerging low power systems for the internet-of-things. A dynamic energy-accuracy trade-off brings an extra degree of freedom for system level power management. We introduce the concept of Dynamic Voltage Accuracy Scaling and illustrate its analogy to Dynamic Voltage Frequency Scaling. Dynamic Voltage Accuracy Scaling proves to have higher energy gains at most output qualities compared to other approximate computing alternatives. This work further generalizes the Dynamic Voltage Accuracy Scaling concept to pipelined structures and quantifies its energy overhead. Shallow pipelined multipliers with two to four dynamic accuracy modes can be supported with limited (<; 10-20%) overhead, resulting in significant energy savings of up to 90% or more for less than 2% mean error. DVAS is finally applied to a JPEG image processing application, demonstrating large system level gains without noticeable impact to user or application.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128492508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273525
Chih-Kai Kang, Chun-Han Lin, P. Hsiu
Mobile systems will increasingly feature emerging OLED displays, whose power consumption is highly dependent on the image content. Existing OLED power-saving techniques change users' visual experience or degrade images' visual quality in exchange for power reduction, or seek a chance to also enhance image quality by employing a compound objective function. This paper presents a win-win scheme that always enhances image quality and reduces power consumption simultaneously. We define metrics to assess the profit and the cost for potential image enhancement and power reduction. Then, we propose algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Finally, the proposed scheme is realized as a practical camera application on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database are very encouraging and provide valuable insights for future research and practices.
{"title":"A win-win camera: Quality-enhanced power-saving images on mobile OLED displays","authors":"Chih-Kai Kang, Chun-Han Lin, P. Hsiu","doi":"10.1109/ISLPED.2015.7273525","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273525","url":null,"abstract":"Mobile systems will increasingly feature emerging OLED displays, whose power consumption is highly dependent on the image content. Existing OLED power-saving techniques change users' visual experience or degrade images' visual quality in exchange for power reduction, or seek a chance to also enhance image quality by employing a compound objective function. This paper presents a win-win scheme that always enhances image quality and reduces power consumption simultaneously. We define metrics to assess the profit and the cost for potential image enhancement and power reduction. Then, we propose algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Finally, the proposed scheme is realized as a practical camera application on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database are very encouraging and provide valuable insights for future research and practices.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130395687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273494
Georgios Zervakis, S. Xydis, Kostas Tsoumanis, D. Soudris, K. Pekmestzi
Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.
{"title":"Hybrid approximate multiplier architectures for improved power-accuracy trade-offs","authors":"Georgios Zervakis, S. Xydis, Kostas Tsoumanis, D. Soudris, K. Pekmestzi","doi":"10.1109/ISLPED.2015.7273494","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273494","url":null,"abstract":"Approximate computing forms a promising design alternative for inherently error resilient applications, trading accuracy for power savings. In this paper, we exploit multi-level approximation, i.e. at the algorithmic, the logic and the circuit level, to design low power approximate arithmetic architectures for hardware multipliers. Motivated from the limited power savings that approximation techniques can achieve in isolation, we explore hybrid methods that apply simultaneously more than one techniques from different layers. We introduce the concept of perforation for approximate arithmetic circuit design and we explore the newly defined design space of hybrid designs showing that it leads to lower power consumption at every examined error range. To address the increased complexity of the target design space, we introduce an heuristic optimization technique and the corresponding design framework that automatically generates hybrid low-power approximate multipliers requiring a small number of design evaluations, i.e. synthesis, simulation, power and timing analysis. Through extensive experimentation, we show that the proposed techniques converge towards optimal solutions and deliver approximate designs that are always more efficient with respect to state-of-art approaches. Power savings of 11% are reported for small error bounds and more than 30% in case of more relaxed error constraints.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129142462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273493
D. May, W. Stechele
Approximate Computing has recently drawn interest due to its promise to substantially decrease the power consumption of integrated circuits. By tolerating a certain imprecision at a circuit output, the circuit can be operated at a more resource-saving state. For instance, parts of the circuit could be switched off or driven at sub-threshold voltage. Clearly, not all applications are suitable for this approach. Especially applications from the signal and image processing domain are applicable, due to their intrinsic tolerance to imprecision. But even for these circuits, one has to be very careful where to approximate a circuit and to what extent, in order not to fall below a minimum required QoS. In this paper we are presenting an approach to generate approximate circuits from existing deterministic implementations. The flow reaches from application-driven QoS definition down to approximated RTL. We are employing FPGA-based fault emulation of the circuit in order to find out how faults, i.e. imprecisions in the circuit, affect the overall circuit behavior. Most existing approaches only consider combinational circuits. Our proposed methodology is able to approximate complete sequential circuits. Due to the FPGA-based emulation, our approach is very fast and accurate. And furthermore, it allows us to fine-granular tune the resulting precision to the required QoS, in order to get the most out of the approximation.
{"title":"Design of fine-grained sequential approximate circuits using probability-aware fault emulation","authors":"D. May, W. Stechele","doi":"10.1109/ISLPED.2015.7273493","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273493","url":null,"abstract":"Approximate Computing has recently drawn interest due to its promise to substantially decrease the power consumption of integrated circuits. By tolerating a certain imprecision at a circuit output, the circuit can be operated at a more resource-saving state. For instance, parts of the circuit could be switched off or driven at sub-threshold voltage. Clearly, not all applications are suitable for this approach. Especially applications from the signal and image processing domain are applicable, due to their intrinsic tolerance to imprecision. But even for these circuits, one has to be very careful where to approximate a circuit and to what extent, in order not to fall below a minimum required QoS. In this paper we are presenting an approach to generate approximate circuits from existing deterministic implementations. The flow reaches from application-driven QoS definition down to approximated RTL. We are employing FPGA-based fault emulation of the circuit in order to find out how faults, i.e. imprecisions in the circuit, affect the overall circuit behavior. Most existing approaches only consider combinational circuits. Our proposed methodology is able to approximate complete sequential circuits. Due to the FPGA-based emulation, our approach is very fast and accurate. And furthermore, it allows us to fine-granular tune the resulting precision to the required QoS, in order to get the most out of the approximation.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123454652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273542
A. Varma, W. Bowhill, Jason Crop, Corey Gough, B. Griffith, Dan Kingsley, K. Sistla
The Intel Xeon E5 v3 family is the latest generation of enterprise-grade, high-performance, Xeon microprocessors. It implements several new power-management technologies and features aimed at improving power/performance efficiency, increasing performance, and improving power delivery. It is the first commercial x86 processor to manage voltage/frequency optimizations on a per-core granularity. This is done by combining a) fine-grained on-die per-core voltage regulators, enabling every core on the processor to run at a different voltage, b) per-core clock management, enabling each core to run at a different frequency, and c) advanced power management algorithms for optimizing the frequency and voltage of each core based on OS requests, system utilization, on-die sensors, and silicon characteristics. The Xeon E5 v3 family also introduces a new maximum-power-draw (Pmax) management approach. This paper describes some of the technical challenges, solutions, and lessons learned during the architecture, design, and productization of this new generation of microprocessor architecture, as well as the power/performance improvements measured for server workloads.
{"title":"Power management in the Intel Xeon E5 v3","authors":"A. Varma, W. Bowhill, Jason Crop, Corey Gough, B. Griffith, Dan Kingsley, K. Sistla","doi":"10.1109/ISLPED.2015.7273542","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273542","url":null,"abstract":"The Intel Xeon E5 v3 family is the latest generation of enterprise-grade, high-performance, Xeon microprocessors. It implements several new power-management technologies and features aimed at improving power/performance efficiency, increasing performance, and improving power delivery. It is the first commercial x86 processor to manage voltage/frequency optimizations on a per-core granularity. This is done by combining a) fine-grained on-die per-core voltage regulators, enabling every core on the processor to run at a different voltage, b) per-core clock management, enabling each core to run at a different frequency, and c) advanced power management algorithms for optimizing the frequency and voltage of each core based on OS requests, system utilization, on-die sensors, and silicon characteristics. The Xeon E5 v3 family also introduces a new maximum-power-draw (Pmax) management approach. This paper describes some of the technical challenges, solutions, and lessons learned during the architecture, design, and productization of this new generation of microprocessor architecture, as well as the power/performance improvements measured for server workloads.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130205833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273511
Jun Luan, Seung Jae Lee, P. Chou
Sternocleidomastoid (SCM) is a paired muscle that stretches along both sides of the neck area. It acts as an accessory muscle of inhalation. Abnormal SCM contraction during asthma is usually a sign of further respiratory impairment. Thus, monitoring SCM muscles has great significance in asthma assessment and control. In this work, we develop a wearable monitoring system based on an optical sensor that consists of an LED and a photo detector (PD). A voltage comparator enables the microcontroller unit (MCU) to remain in sleep mode until waken upon detecting contraction. Experimental results show that our optical sensor consumes much lower power than surface electromyography (sEMG), the most commonly used technique while offering more comfort and compactness. It is also robust to motion artifact and DC baseline wandering. These properties simplify the hardware design, while the use of the comparator further reduces the system power consumption to >450 μW on average, making it the best option for low power monitoring.
{"title":"Low-power detection of sternocleidomastoid muscle contraction for asthma assessment and control","authors":"Jun Luan, Seung Jae Lee, P. Chou","doi":"10.1109/ISLPED.2015.7273511","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273511","url":null,"abstract":"Sternocleidomastoid (SCM) is a paired muscle that stretches along both sides of the neck area. It acts as an accessory muscle of inhalation. Abnormal SCM contraction during asthma is usually a sign of further respiratory impairment. Thus, monitoring SCM muscles has great significance in asthma assessment and control. In this work, we develop a wearable monitoring system based on an optical sensor that consists of an LED and a photo detector (PD). A voltage comparator enables the microcontroller unit (MCU) to remain in sleep mode until waken upon detecting contraction. Experimental results show that our optical sensor consumes much lower power than surface electromyography (sEMG), the most commonly used technique while offering more comfort and compactness. It is also robust to motion artifact and DC baseline wandering. These properties simplify the hardware design, while the use of the comparator further reduces the system power consumption to >450 μW on average, making it the best option for low power monitoring.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133143075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273488
W. Yueh, Z. Wan, Y. Joshi, S. Mukhopadhyay
This paper, for the first time, experimentally demonstrated the in-package microfluidic cooling on a commercial System-on-Chip (SoC). The pinfin interposer attached to the commercial SoC achieved energy efficient cooling for the SPLASH-2 benchmark suite in measurement. The low-power piezoelectric pump controlled by the SoC ensures the thermal integrity and reduces the system-level energy consumption through leakage reduction. The measurements demonstrated that the in-package fluidic cooling improves the SoC's energy-efficiency and reduces design footprint compared to the external passive cooling.
{"title":"Experimental characterization of in-package microfluidic cooling on a System-on-Chip","authors":"W. Yueh, Z. Wan, Y. Joshi, S. Mukhopadhyay","doi":"10.1109/ISLPED.2015.7273488","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273488","url":null,"abstract":"This paper, for the first time, experimentally demonstrated the in-package microfluidic cooling on a commercial System-on-Chip (SoC). The pinfin interposer attached to the commercial SoC achieved energy efficient cooling for the SPLASH-2 benchmark suite in measurement. The low-power piezoelectric pump controlled by the SoC ensures the thermal integrity and reduces the system-level energy consumption through leakage reduction. The measurements demonstrated that the in-package fluidic cooling improves the SoC's energy-efficiency and reduces design footprint compared to the external passive cooling.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273539
K. Vatanparvar, Jiang Wan, M. A. Faruque
Recently, Electric Vehicles (EVs) have been considered as new paradigm of transportation in order to solve environmental concerns, e.g. air pollution. However, EVs pose new challenges regarding their Battery LifeTime (BLT), energy consumption, and energy costs related to battery charging. The EV power consumption may be estimated by having the route information and the EV specifications. Also, by having the battery characteristics, the battery capacity consumption and the BLT may be estimated for each route. In this paper, we propose a driving management which uses the above-mentioned information in order to optimize the driving route by being aware of the EV energy consumption, energy cost, and BLT. Our proposed driving management extends the BLT by 16.8% and reduces the energy consumption by 11.9% and energy cost by 12.6% on average, by selecting the optimized route instead of the fastest route.
{"title":"Battery-aware energy-optimal Electric Vehicle driving management","authors":"K. Vatanparvar, Jiang Wan, M. A. Faruque","doi":"10.1109/ISLPED.2015.7273539","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273539","url":null,"abstract":"Recently, Electric Vehicles (EVs) have been considered as new paradigm of transportation in order to solve environmental concerns, e.g. air pollution. However, EVs pose new challenges regarding their Battery LifeTime (BLT), energy consumption, and energy costs related to battery charging. The EV power consumption may be estimated by having the route information and the EV specifications. Also, by having the battery characteristics, the battery capacity consumption and the BLT may be estimated for each route. In this paper, we propose a driving management which uses the above-mentioned information in order to optimize the driving route by being aware of the EV energy consumption, energy cost, and BLT. Our proposed driving management extends the BLT by 16.8% and reduces the energy consumption by 11.9% and energy cost by 12.6% on average, by selecting the optimized route instead of the fastest route.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123485150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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