Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273504
Xiaoyang Mi, Debashis Mandal, V. Sathe, B. Bakkaloglu, Jae-sun Seo
Efficient, stable, and fast power delivery against fluctuating workloads have become a critical concern for applications from battery-powered devices to high-performance servers. With high density on-chip capacitors, fully-integrated switched-capacitor (SC) voltage converters provide high efficiency down-conversion from a battery or off-chip voltage regulation modules. However, maintaining such efficiency with minimal supply noise across a wide range of fluctuating load currents remains challenging. In this paper, we propose an on-chip current sensing technique to dynamically modulate both switching frequency and switch widths of SC voltage converters, enhancing fast transient response and higher efficiency across a wide range of load currents. In conjunction with SC converters, we employ a low-dropout regulator (LDO) driven by a push-pull operational transconductance amplifier (OTA), whose current is mirrored and sensed with minimal power and efficiency overhead. The sensed load current directly controls the frequency and width of SC converters through a voltage-controlled oscillator (VCO) and a time-to-digital converter, respectively. In 32nm SOI CMOS, the proposed voltage regulator maintains 77-82% efficiency at 0.95V output voltage with less than 20mV steady-state ripple across 10X load current range of 100mA-1A and 33mV droop voltage for a 80mA/ns load transition, while providing a projected current density of 6W/mm2.
针对波动的工作负载，高效、稳定和快速的供电已经成为从电池供电设备到高性能服务器等应用程序的关键问题。采用高密度片上电容器，完全集成的开关电容器(SC)电压变换器从电池或片外电压调节模块提供高效率的下转换。然而，在大范围的波动负载电流下保持这样的效率和最小的电源噪声仍然是一个挑战。在本文中，我们提出了一种片上电流传感技术来动态调制SC电压变换器的开关频率和开关宽度，从而在大范围的负载电流范围内增强快速瞬态响应和更高的效率。与SC转换器一起，我们采用了由推挽式跨导放大器(OTA)驱动的低差稳压器(LDO)，其电流以最小的功率和效率开销进行镜像和检测。检测到的负载电流分别通过压控振荡器(VCO)和时间数字转换器直接控制SC变换器的频率和宽度。在32nm SOI CMOS中，该稳压器在0.95V输出电压下保持77-82%的效率，在100mA-1A的10倍负载电流范围内保持小于20mV的稳态纹波，在80mA/ns负载转换时提供33mV的下垂电压，同时提供6W/mm2的投射电流密度。
{"title":"Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS","authors":"Xiaoyang Mi, Debashis Mandal, V. Sathe, B. Bakkaloglu, Jae-sun Seo","doi":"10.1109/ISLPED.2015.7273504","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273504","url":null,"abstract":"Efficient, stable, and fast power delivery against fluctuating workloads have become a critical concern for applications from battery-powered devices to high-performance servers. With high density on-chip capacitors, fully-integrated switched-capacitor (SC) voltage converters provide high efficiency down-conversion from a battery or off-chip voltage regulation modules. However, maintaining such efficiency with minimal supply noise across a wide range of fluctuating load currents remains challenging. In this paper, we propose an on-chip current sensing technique to dynamically modulate both switching frequency and switch widths of SC voltage converters, enhancing fast transient response and higher efficiency across a wide range of load currents. In conjunction with SC converters, we employ a low-dropout regulator (LDO) driven by a push-pull operational transconductance amplifier (OTA), whose current is mirrored and sensed with minimal power and efficiency overhead. The sensed load current directly controls the frequency and width of SC converters through a voltage-controlled oscillator (VCO) and a time-to-digital converter, respectively. In 32nm SOI CMOS, the proposed voltage regulator maintains 77-82% efficiency at 0.95V output voltage with less than 20mV steady-state ripple across 10X load current range of 100mA-1A and 33mV droop voltage for a 80mA/ns load transition, while providing a projected current density of 6W/mm2.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116625737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273482
Seyedhamidreza Motaman, Swaroop Ghosh, J. Kulkarni
Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. We propose a novel slope detection technique to exploit MTJ resistance switching from high to low state using low-overhead sample-and-hold circuit. The proposed sensing technique is destructive in nature and can be combined with double sampling for improved robustness. Simulation results reveal <;0.12% failure under process variation using single sampling (at 0.2% area overhead) and <;0.08% failures with double sampling (at 0.6% area overhead). The overall sense time is found to be 6.8ns.
{"title":"A novel slope detection technique for robust STTRAM sensing","authors":"Seyedhamidreza Motaman, Swaroop Ghosh, J. Kulkarni","doi":"10.1109/ISLPED.2015.7273482","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273482","url":null,"abstract":"Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection of data and reference currents. We propose a novel slope detection technique to exploit MTJ resistance switching from high to low state using low-overhead sample-and-hold circuit. The proposed sensing technique is destructive in nature and can be combined with double sampling for improved robustness. Simulation results reveal <;0.12% failure under process variation using single sampling (at 0.2% area overhead) and <;0.08% failures with double sampling (at 0.6% area overhead). The overall sense time is found to be 6.8ns.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114043123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273527
A. Romani, Antonio Camarda, A. Baldazzi, M. Tartagni
This paper introduces the use of piezoelectric transformers (PTs) as key elements for ultra-low voltage start-up circuits for battery-less energy harvesting applications. Firstly, a step-up oscillator topology based on a PT and a JFET is presented. The circuit is able to start from voltages as low as 16 mV, and to boost the output voltage up to 1.32 V in a no load condition. In order to validate the proposed approach, a surrounding power management and conversion circuit is developed. This circuit is able to automatically enable a boost DC/DC converter once the start-up circuit has generated a sufficient voltage. The whole circuit self-starts with an input voltage of 30 mV, and the maximum conversion efficiency referred to the maximum power point (MPP) is higher than 40%, with an intrinsic current consumption as low as 1.3 μA.
{"title":"A micropower energy harvesting circuit with piezoelectric transformer-based ultra-low voltage start-up","authors":"A. Romani, Antonio Camarda, A. Baldazzi, M. Tartagni","doi":"10.1109/ISLPED.2015.7273527","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273527","url":null,"abstract":"This paper introduces the use of piezoelectric transformers (PTs) as key elements for ultra-low voltage start-up circuits for battery-less energy harvesting applications. Firstly, a step-up oscillator topology based on a PT and a JFET is presented. The circuit is able to start from voltages as low as 16 mV, and to boost the output voltage up to 1.32 V in a no load condition. In order to validate the proposed approach, a surrounding power management and conversion circuit is developed. This circuit is able to automatically enable a boost DC/DC converter once the start-up circuit has generated a sufficient voltage. The whole circuit self-starts with an input voltage of 30 mV, and the maximum conversion efficiency referred to the maximum power point (MPP) is higher than 40%, with an intrinsic current consumption as low as 1.3 μA.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117304305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273514
Kyungwook Chang, Kartik Acharya, S. Sinha, B. Cline, G. Yeric, S. Lim
Monolithic 3D IC (M3D) is one potential technology to help with the challenges of continued circuit power and performance scaling. In this paper, for the first time, the power benefits of monolithic 3D IC (M3D) using a 7nm FinFET technology are investigated. The predictive 7nm Process Design Kit (PDK) and standard cell library for both high performance (HP) and low standby power (LSTP) device technologies are built based on NanGate 45nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. In addition, we implement full-chip M3D GDS layouts using both 7nm HP and LSTP cells and industry-standard physical design tools, and evaluate the resulting full-chip power, performance, and area metrics. Our study first shows that 7nm HP M3D designs outperform 7nm HP 2D designs by 16.8% in terms of iso-performance total power reduction. Moreover, 7nm LSTP M3D designs reduce the total power consumption by 14.3% compared to their 2D counterparts. This convincingly demonstrates the power benefits of M3D technologies in both high performance as well as low power future generation devices.
单片3D集成电路(M3D)是一种潜在的技术，可以帮助解决持续电路功率和性能扩展的挑战。本文首次对采用7nm FinFET技术的单片3D集成电路(M3D)的功耗效益进行了研究。用于高性能(HP)和低待机功率(LSTP)器件技术的预测性7nm工艺设计套件(PDK)和标准单元库是基于NanGate 45nm PDK构建的，使用出版物和商业级工具流程中的精确尺寸，材料和电气参数。此外，我们还使用7nm HP和LSTP单元以及行业标准物理设计工具实现了全芯片M3D GDS布局，并评估了由此产生的全芯片功耗、性能和面积指标。我们的研究首先表明，在同等性能的总功耗降低方面，7nm HP M3D设计比7nm HP 2D设计高出16.8%。此外，7nm LSTP M3D设计与2D设计相比，总功耗降低了14.3%。这令人信服地证明了M3D技术在高性能和低功耗未来一代设备中的功率优势。
{"title":"Power benefit study of monolithic 3D IC at the 7nm technology node","authors":"Kyungwook Chang, Kartik Acharya, S. Sinha, B. Cline, G. Yeric, S. Lim","doi":"10.1109/ISLPED.2015.7273514","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273514","url":null,"abstract":"Monolithic 3D IC (M3D) is one potential technology to help with the challenges of continued circuit power and performance scaling. In this paper, for the first time, the power benefits of monolithic 3D IC (M3D) using a 7nm FinFET technology are investigated. The predictive 7nm Process Design Kit (PDK) and standard cell library for both high performance (HP) and low standby power (LSTP) device technologies are built based on NanGate 45nm PDK using accurate dimensional, material, and electrical parameters from publications and a commercial-grade tool flow. In addition, we implement full-chip M3D GDS layouts using both 7nm HP and LSTP cells and industry-standard physical design tools, and evaluate the resulting full-chip power, performance, and area metrics. Our study first shows that 7nm HP M3D designs outperform 7nm HP 2D designs by 16.8% in terms of iso-performance total power reduction. Moreover, 7nm LSTP M3D designs reduce the total power consumption by 14.3% compared to their 2D counterparts. This convincingly demonstrates the power benefits of M3D technologies in both high performance as well as low power future generation devices.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126584589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273496
Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok
This paper presents algorithm and digital hardware design, inspired by biological spiking neural networks, to perform unsupervised, online spike-clustering with high accuracy and low-power consumption in the context of deep-brain sensing and stimulation systems. The proposed hardware contains 1220 digital neurons and 4.86k latch-based synapses, and achieves the average sorting accuracy of 91% whereas the conventional hardware based on the Osort algorithm achieves 69% for the same datasets. Implemented in a 65nm high-Vth, the processor exhibits a footprint of 0.25mm2/ch. and a power consumption of 9.3μW/ch. at VDD of 0.3V.
{"title":"A neuromorphic neural spike clustering processor for deep-brain sensing and stimulation systems","authors":"Beinuo Zhang, Zhewei Jiang, Qi Wang, Jae-sun Seo, Mingoo Seok","doi":"10.1109/ISLPED.2015.7273496","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273496","url":null,"abstract":"This paper presents algorithm and digital hardware design, inspired by biological spiking neural networks, to perform unsupervised, online spike-clustering with high accuracy and low-power consumption in the context of deep-brain sensing and stimulation systems. The proposed hardware contains 1220 digital neurons and 4.86k latch-based synapses, and achieves the average sorting accuracy of 91% whereas the conventional hardware based on the Osort algorithm achieves 69% for the same datasets. Implemented in a 65nm high-Vth, the processor exhibits a footprint of 0.25mm2/ch. and a power consumption of 9.3μW/ch. at VDD of 0.3V.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127930709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273484
Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li
Phase-change memory (PCM) has gained much attention recently since it offers several advantages over DRAM, such as high cell density and low leakage power. PCM has similar read power and latency as DRAM; however, its write power and latency are significantly higher than DRAM. Therefore, one challenge with PCM is how to increase write throughput under write power budget constraints. To increase write concurrency, PCM often adopts division programming, where a write occurs in a series of divisions, so that writes to different banks proceed concurrently. In this study, we observe that since the write scheduling granularity in the memory controller differs from the actual write granularity in PCM chips, i.e., requests vs. divisions, the available power budget cannot be fully utilized. We therefore propose enhancing the interface between the memory controller and PCM chips to allow the memory controller to schedule writes in the division granularity. To further increase power budget utilization, we design a variable-length division mechanism to allow the division granularity to be adjusted at runtime according to the available write power budget. Our experimental results show that these techniques improve system performance by up to 65%.
{"title":"Fine-grained write scheduling for PCM performance improvement under write power budget","authors":"Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li","doi":"10.1109/ISLPED.2015.7273484","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273484","url":null,"abstract":"Phase-change memory (PCM) has gained much attention recently since it offers several advantages over DRAM, such as high cell density and low leakage power. PCM has similar read power and latency as DRAM; however, its write power and latency are significantly higher than DRAM. Therefore, one challenge with PCM is how to increase write throughput under write power budget constraints. To increase write concurrency, PCM often adopts division programming, where a write occurs in a series of divisions, so that writes to different banks proceed concurrently. In this study, we observe that since the write scheduling granularity in the memory controller differs from the actual write granularity in PCM chips, i.e., requests vs. divisions, the available power budget cannot be fully utilized. We therefore propose enhancing the interface between the memory controller and PCM chips to allow the memory controller to schedule writes in the division granularity. To further increase power budget utilization, we design a variable-length division mechanism to allow the division granularity to be adjusted at runtime according to the available write power budget. Our experimental results show that these techniques improve system performance by up to 65%.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125676182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273538
H. Amrouch, J. Henkel
Thermal analysis is a prerequisite for developing reliability increasing techniques for thermally-constrained processors, i.e. processors with a high power density. For that purpose, infrared (IR) camera measurement setups have been deployed with the purpose to provide direct feedback of the impact that thermal mitigation techniques have. To obtain lucid IR images1, the IR-opaque cooling must be removed and hence, an alternative IR-transparent cooling needs to be provided to protect the chip. To this end, the majority of state-of-the-art employs an IR coolant liquid to prevent the chip from overheating. The problem is that several aspects like thermal convection may interfere with the measured IR radiations resulting in equivocal IR images. Thus, they decrease the accuracy in a way that leads to incorrectly estimating reliability. Solving this prominent problem, we introduce an IR-transparent cooling that cools the chip from its rear side allowing the camera to perspicuously capture the IR emissions as no additional layer in between impedes the radiation. It maintains the on-chip temperatures within a safe range equivalent to the original heat sink-based cooling. We demonstrate how state-of-the-art inaccurate thermal analysis results in incorrectly estimating reliability. Our setup is the most accurate, least intrusive one that has been both proposed and actually applied to state-of-the-art multi-cores (Intel 45nm dual-core and 22nm octa-core).
{"title":"Lucid infrared thermography of thermally-constrained processors","authors":"H. Amrouch, J. Henkel","doi":"10.1109/ISLPED.2015.7273538","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273538","url":null,"abstract":"Thermal analysis is a prerequisite for developing reliability increasing techniques for thermally-constrained processors, i.e. processors with a high power density. For that purpose, infrared (IR) camera measurement setups have been deployed with the purpose to provide direct feedback of the impact that thermal mitigation techniques have. To obtain lucid IR images1, the IR-opaque cooling must be removed and hence, an alternative IR-transparent cooling needs to be provided to protect the chip. To this end, the majority of state-of-the-art employs an IR coolant liquid to prevent the chip from overheating. The problem is that several aspects like thermal convection may interfere with the measured IR radiations resulting in equivocal IR images. Thus, they decrease the accuracy in a way that leads to incorrectly estimating reliability. Solving this prominent problem, we introduce an IR-transparent cooling that cools the chip from its rear side allowing the camera to perspicuously capture the IR emissions as no additional layer in between impedes the radiation. It maintains the on-chip temperatures within a safe range equivalent to the original heat sink-based cooling. We demonstrate how state-of-the-art inaccurate thermal analysis results in incorrectly estimating reliability. Our setup is the most accurate, least intrusive one that has been both proposed and actually applied to state-of-the-art multi-cores (Intel 45nm dual-core and 22nm octa-core).","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273537
M. Dousti, Majid Ghasemi-Gol, M. Nazemi, M. Pedram
This paper introduces ThermTap, which enables system and software developers to monitor the power consumption and temperature of various hardware components in an Android device as a function of running applications and processes. ThermTap comprises of a power analyzer, called PowerTap, and an online thermal simulator, called Therminator 2. With accurate power macro-models, PowerTap collates activity profiles of major components of a portable device from the OS kernel device drivers in an event-driven manner to generate power traces. In turn, Therminator 2 reads these traces and, using a compact thermal model of the device, generates various temperature maps including those for the device components and device skin. Fast thermal simulation techniques enable Therminator 2 to be executed in realtime. With precise per-process and per-application temperature maps that ThermTap produces, it enables software and system developers to find thermal bugs in their software. A case study is presented on identifying a thermal bug in the software running on an Android device.
{"title":"ThermTap: An online power analyzer and thermal simulator for Android devices","authors":"M. Dousti, Majid Ghasemi-Gol, M. Nazemi, M. Pedram","doi":"10.1109/ISLPED.2015.7273537","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273537","url":null,"abstract":"This paper introduces ThermTap, which enables system and software developers to monitor the power consumption and temperature of various hardware components in an Android device as a function of running applications and processes. ThermTap comprises of a power analyzer, called PowerTap, and an online thermal simulator, called Therminator 2. With accurate power macro-models, PowerTap collates activity profiles of major components of a portable device from the OS kernel device drivers in an event-driven manner to generate power traces. In turn, Therminator 2 reads these traces and, using a compact thermal model of the device, generates various temperature maps including those for the device components and device skin. Fast thermal simulation techniques enable Therminator 2 to be executed in realtime. With precise per-process and per-application temperature maps that ThermTap produces, it enables software and system developers to find thermal bugs in their software. A case study is presented on identifying a thermal bug in the software running on an Android device.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273535
V. Sathe, Jae-sun Seo
Energy-efficiency continues to limit peak computational performance in digital systems. To drive continued energy-improvements, designers of modern digital systems are relying on multiple, smaller voltage domains for enhanced voltage-scaling. Switched-capacitor (SC) voltage converters are a promising alternative to traditional switched-inductor regulators due to their suitability for efficient, fully-integrated regulation of finer voltage domains. However, several important problems regarding the analysis and optimization of SC converter design remain unaddressed. This paper develops a comprehensive analysis of SC converter output resistance to establish the optimal switching frequency and switch resistance for maximum converter efficiency. The proposed analysis is validated through simulation experiments conducted using an industrial 65nm CMOS technology.
{"title":"Analysis and optimization of CMOS switched-capacitor converters","authors":"V. Sathe, Jae-sun Seo","doi":"10.1109/ISLPED.2015.7273535","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273535","url":null,"abstract":"Energy-efficiency continues to limit peak computational performance in digital systems. To drive continued energy-improvements, designers of modern digital systems are relying on multiple, smaller voltage domains for enhanced voltage-scaling. Switched-capacitor (SC) voltage converters are a promising alternative to traditional switched-inductor regulators due to their suitability for efficient, fully-integrated regulation of finer voltage domains. However, several important problems regarding the analysis and optimization of SC converter design remain unaddressed. This paper develops a comprehensive analysis of SC converter output resistance to establish the optimal switching frequency and switch resistance for maximum converter efficiency. The proposed analysis is validated through simulation experiments conducted using an industrial 65nm CMOS technology.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129993577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273501
Hao He, Jiafan Wang, Jiang Hu
Adaptive design is a power-efficient approach to variation resilience in VLSI circuits. However, its implementation, especially that of fine-grained adaptivity, can easily result in large overhead. Although numerous previous works have demonstrated the effectiveness of adaptive design, very few works have emphasized its overhead control. In order to make adaptive design a truly practical approach, we develop a method that systematically optimizes adaptivity assignment with consideration of overhead reduction. At the same time, a variability aware gate implementation selection technique is investigated and applied in conjunction with the adaptivity assignment. Experimental results on benchmark circuits indicate that our approach can greatly decrease adaptivity overhead while satisfy performance and robustness constraints.
{"title":"Collaborative gate implementation selection and adaptivity assignment for robust combinational circuits","authors":"Hao He, Jiafan Wang, Jiang Hu","doi":"10.1109/ISLPED.2015.7273501","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273501","url":null,"abstract":"Adaptive design is a power-efficient approach to variation resilience in VLSI circuits. However, its implementation, especially that of fine-grained adaptivity, can easily result in large overhead. Although numerous previous works have demonstrated the effectiveness of adaptive design, very few works have emphasized its overhead control. In order to make adaptive design a truly practical approach, we develop a method that systematically optimizes adaptivity assignment with consideration of overhead reduction. At the same time, a variability aware gate implementation selection technique is investigated and applied in conjunction with the adaptivity assignment. Experimental results on benchmark circuits indicate that our approach can greatly decrease adaptivity overhead while satisfy performance and robustness constraints.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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