Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273522
Mohammad Sadrosadati, Amirhossein Mirhosseini, Homa Aghilinasab, H. Sarbazi-Azad
Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to reduce the power consumption. By using this method, we manage to save power by up to 45.7% compared to a baseline architecture without any performance loss.
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Pub Date : 2015-07-22DOI: 10.1109/ISLPED.2015.7273505
Shidhartha Das, P. Whatmough, David M. Bull
Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make these systems susceptible to pathological AC transients. Consequently, mobile computing systems are ultimately limited by power-delivery. In this paper, we present the system-level Power Delivery Network (PDN) modeling, analysis and measurement results on a dual-core 64bit ARM Cortex-A57 compute cluster in 28nm CMOS. We present a comprehensive analysis of the PDN by characterizing the individual contribution of each constituent i.e. the PCB, package and the die. We present frequency- and time-domain simulation results and correlate that with measurement (both on-chip and off-chip). Our results demonstrate how complex software and micro-architectural interactions can trigger PDN resonances that ultimately lead to system failure.
{"title":"Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS","authors":"Shidhartha Das, P. Whatmough, David M. Bull","doi":"10.1109/ISLPED.2015.7273505","DOIUrl":"https://doi.org/10.1109/ISLPED.2015.7273505","url":null,"abstract":"Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make these systems susceptible to pathological AC transients. Consequently, mobile computing systems are ultimately limited by power-delivery. In this paper, we present the system-level Power Delivery Network (PDN) modeling, analysis and measurement results on a dual-core 64bit ARM Cortex-A57 compute cluster in 28nm CMOS. We present a comprehensive analysis of the PDN by characterizing the individual contribution of each constituent i.e. the PCB, package and the die. We present frequency- and time-domain simulation results and correlate that with measurement (both on-chip and off-chip). Our results demonstrate how complex software and micro-architectural interactions can trigger PDN resonances that ultimately lead to system failure.","PeriodicalId":421236,"journal":{"name":"2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132146702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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