Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_16
A. Ortiz, L. Indrusiak
{"title":"Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip","authors":"A. Ortiz, L. Indrusiak","doi":"10.1007/978-3-642-17752-1_16","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_16","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124960650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_13
Mohsen Raji, A. Tajary, B. Ghavami, H. Pedram, H. Zarandi
{"title":"Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations","authors":"Mohsen Raji, A. Tajary, B. Ghavami, H. Pedram, H. Zarandi","doi":"10.1007/978-3-642-17752-1_13","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_13","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124603074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_2
Christian Bachmann, Andreas Genser, C. Steger, R. Weiss, J. Haid
{"title":"An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software","authors":"Christian Bachmann, Andreas Genser, C. Steger, R. Weiss, J. Haid","doi":"10.1007/978-3-642-17752-1_2","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_2","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133315370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_9
C. Lazzari, J. Fernandes, P. Flores, J. Monteiro
{"title":"An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs","authors":"C. Lazzari, J. Fernandes, P. Flores, J. Monteiro","doi":"10.1007/978-3-642-17752-1_9","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_9","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124122715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_27
F. Pêcheux, Khouloud Zine el Abidine, A. Greiner
{"title":"Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS","authors":"F. Pêcheux, Khouloud Zine el Abidine, A. Greiner","doi":"10.1007/978-3-642-17752-1_27","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_27","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127589534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_18
M. Lanuzza, R. Rose, F. Frustaci, S. Perri, P. Corsonello
{"title":"Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis","authors":"M. Lanuzza, R. Rose, F. Frustaci, S. Perri, P. Corsonello","doi":"10.1007/978-3-642-17752-1_18","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_18","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115854610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_31
M. Belleville
{"title":"3D Integration for Digital and Imagers Circuits: Opportunities and Challenges","authors":"M. Belleville","doi":"10.1007/978-3-642-17752-1_31","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_31","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_17
B. K. Boroujeni, C. Piguet, Y. Leblebici
{"title":"Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing","authors":"B. K. Boroujeni, C. Piguet, Y. Leblebici","doi":"10.1007/978-3-642-17752-1_17","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_17","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130706831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_20
Christoph Knoth, I. Eichwald, P. Nordholz, Ulf Schlichtmann
{"title":"White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation","authors":"Christoph Knoth, I. Eichwald, P. Nordholz, Ulf Schlichtmann","doi":"10.1007/978-3-642-17752-1_20","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_20","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"9 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134352416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_30
K. Itoh
{"title":"Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs","authors":"K. Itoh","doi":"10.1007/978-3-642-17752-1_30","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_30","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"112 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114115319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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