Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_19
Qin Tang, A. Zjajo, Michel Berkelaar, N. V. D. Meijs
{"title":"Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations","authors":"Qin Tang, A. Zjajo, Michel Berkelaar, N. V. D. Meijs","doi":"10.1007/978-3-642-17752-1_19","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_19","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_14
Oussama Elissati, E. Yahya, Sébastien Rieubon, L. Fesquet
{"title":"Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case","authors":"Oussama Elissati, E. Yahya, Sébastien Rieubon, L. Fesquet","doi":"10.1007/978-3-642-17752-1_14","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_14","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131882198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_29
L. Maillet-Contoz
{"title":"OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCs","authors":"L. Maillet-Contoz","doi":"10.1007/978-3-642-17752-1_29","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_29","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132634892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_25
Jan Haase, C. Grimm
{"title":"Power Profiling of Embedded Analog/Mixed-Signal Systems","authors":"Jan Haase, C. Grimm","doi":"10.1007/978-3-642-17752-1_25","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_25","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_32
Sébastien Marchal
{"title":"Signing Off Industrial Designs on Evolving Technologies","authors":"Sébastien Marchal","doi":"10.1007/978-3-642-17752-1_32","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_32","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_23
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham
{"title":"Clock Network Synthesis with Concurrent Gate Insertion","authors":"Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham","doi":"10.1007/978-3-642-17752-1_23","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_23","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130855314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_7
M. Alioto, Elio Consoli, G. Palumbo
{"title":"Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits","authors":"M. Alioto, Elio Consoli, G. Palumbo","doi":"10.1007/978-3-642-17752-1_7","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_7","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126191983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_10
P. Vivet, E. Beigné, H. Lebreton, N. Zergainoh
{"title":"On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS","authors":"P. Vivet, E. Beigné, H. Lebreton, N. Zergainoh","doi":"10.1007/978-3-642-17752-1_10","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_10","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_22
O. Schrape, F. Winkler, Steffen Zeidler, Markus Petri, E. Grass, U. Jagdhold
{"title":"An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis","authors":"O. Schrape, F. Winkler, Steffen Zeidler, Markus Petri, E. Grass, U. Jagdhold","doi":"10.1007/978-3-642-17752-1_22","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_22","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-09-07DOI: 10.1007/978-3-642-17752-1_8
D. Bekiaris, A. Papanikolaou, C. Papameletis, D. Soudris, G. Economakos, K. Pekmestzi
{"title":"A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework","authors":"D. Bekiaris, A. Papanikolaou, C. Papameletis, D. Soudris, G. Economakos, K. Pekmestzi","doi":"10.1007/978-3-642-17752-1_8","DOIUrl":"https://doi.org/10.1007/978-3-642-17752-1_8","url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124550312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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