Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862032
Michail Noltsis, Nikolaos Zambelis, F. Catthoor, D. Soudris
In the era of nanoelectronic circuits, temperature largely affects reliability and static power consumption of systems. In fact, temperature control in modern circuits is considered as a crucial system function, along with low-power operation. To this end, numerous thermal management approaches exist on the hardware, firmware and software layer. A widely used technique for that matter is dynamic voltage and frequency scaling (DVFS), aiming to control temperature by proper voltage and frequency decisions. CPU hot-plug is another technique brought from reliability and fault-tolerance domain that can be utilized for thermal management purposes. To this end, our work examines the thermal profile of an NXP IMX6Q board when different DVFS and CPU hot-plug actuations are applied. In addition, we move further and propose a synergy between the two methods while studying their effect on chip temperature, performance and energy consumption.
{"title":"A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems","authors":"Michail Noltsis, Nikolaos Zambelis, F. Catthoor, D. Soudris","doi":"10.1109/PATMOS.2019.8862032","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862032","url":null,"abstract":"In the era of nanoelectronic circuits, temperature largely affects reliability and static power consumption of systems. In fact, temperature control in modern circuits is considered as a crucial system function, along with low-power operation. To this end, numerous thermal management approaches exist on the hardware, firmware and software layer. A widely used technique for that matter is dynamic voltage and frequency scaling (DVFS), aiming to control temperature by proper voltage and frequency decisions. CPU hot-plug is another technique brought from reliability and fault-tolerance domain that can be utilized for thermal management purposes. To this end, our work examines the thermal profile of an NXP IMX6Q board when different DVFS and CPU hot-plug actuations are applied. In addition, we move further and propose a synergy between the two methods while studying their effect on chip temperature, performance and energy consumption.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862124
Danhui Li, F. Xia, Junwen Luo, A. Yakovlev
For a Switched-Capacitor DC-DC converter (SCC) in a low power design, reversion losses and shoot-through currents may lead to substantial efficiency degradations and voltage reductions at the output. These reversion losses and shoot-through currents are caused by undesired conduction in MOS devices under certain combinations of internal SCC signals including clocks. This paper proposes a new method that models reversion losses and shoot-through currents in SCCs with Petri nets, providing a formal way of tracking them. With reachability analysis on the Petri Net models, reversion losses and shoot-through currents can be verified and investigated, which is helpful for avoiding these problems in designs. This paper takes cross-coupled voltage doublers as examples. Analysis examples where these properties are identified are presented, together with the finding of healthy traces, which do not contain them. Besides tool-supported reachability analysis capabilities, the natural causal event traceability of Petri net models allows the design of SCCs and other analog and mixed signal (AMS) circuits to be more transparent and understandable, and hence easier to reason about, debug and validate.
{"title":"Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets","authors":"Danhui Li, F. Xia, Junwen Luo, A. Yakovlev","doi":"10.1109/PATMOS.2019.8862124","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862124","url":null,"abstract":"For a Switched-Capacitor DC-DC converter (SCC) in a low power design, reversion losses and shoot-through currents may lead to substantial efficiency degradations and voltage reductions at the output. These reversion losses and shoot-through currents are caused by undesired conduction in MOS devices under certain combinations of internal SCC signals including clocks. This paper proposes a new method that models reversion losses and shoot-through currents in SCCs with Petri nets, providing a formal way of tracking them. With reachability analysis on the Petri Net models, reversion losses and shoot-through currents can be verified and investigated, which is helpful for avoiding these problems in designs. This paper takes cross-coupled voltage doublers as examples. Analysis examples where these properties are identified are presented, together with the finding of healthy traces, which do not contain them. Besides tool-supported reachability analysis capabilities, the natural causal event traceability of Petri net models allows the design of SCCs and other analog and mixed signal (AMS) circuits to be more transparent and understandable, and hence easier to reason about, debug and validate.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131084499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862105
Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos
One of the most significant trends in the semiconductor industry is mixed-signal applications. A great amount of effort is focused on creating fast and accurate designs, which include both analog and digital components. As a result, mixed-signal verification poses a major concern. Previous traditional verification techniques offer slow verification time and relatively small robustness. In this work, an efficient UVM-based verification architecture for a digital phase-locked loop (DPLL) real number model using SystemVerilog is presented. The UVM capabilities of the proposed methodology combined with the RNM model of the digital PLL favors the generation of a reusable, time-to-market fast and robust verification environment. Cadence Incisive Enterprise Simulator was used for the testbench creation and simulation. The proposed verification architecture uses constrained-random stimulus generation, analog assertions and coverage metrics, in order to achieve high gains in verification efficiency.
{"title":"UVM-based Verification of a Digital PLL Using SystemVerilog","authors":"Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos","doi":"10.1109/PATMOS.2019.8862105","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862105","url":null,"abstract":"One of the most significant trends in the semiconductor industry is mixed-signal applications. A great amount of effort is focused on creating fast and accurate designs, which include both analog and digital components. As a result, mixed-signal verification poses a major concern. Previous traditional verification techniques offer slow verification time and relatively small robustness. In this work, an efficient UVM-based verification architecture for a digital phase-locked loop (DPLL) real number model using SystemVerilog is presented. The UVM capabilities of the proposed methodology combined with the RNM model of the digital PLL favors the generation of a reusable, time-to-market fast and robust verification environment. Cadence Incisive Enterprise Simulator was used for the testbench creation and simulation. The proposed verification architecture uses constrained-random stimulus generation, analog assertions and coverage metrics, in order to achieve high gains in verification efficiency.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115141490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862128
Shylesh Umapathy, Aaron Stillmaker
With the 54th commemoration of Moores law and the intense development of VLSI technology has permitted more and more IP components to be integrated on a single chip. However, factors such as power consumption has been limiting this growth rate. Low power techniques such as clock gating, power gating, dynamic voltage and frequency scaling, body biasing, and many more have emerged as potential solutions. This paper explores power gating technique and presents the design trade-offs between the ring and grid style of power gate placement in a fine-grained system design. The study used 24 physical designs of 12 different sized MAC units ranging from 44 to 320-bit inputs, and extracted various parameters. The results depict that, using a ring style of placement gives an average increase in IR drop of 9.59% when compared to grid style of placement for 128 to 320-bits input MAC unit. The grid style possesses an additional average congestion of 1.66% when compared to ring style of placement for 192 to 320-bits input MAC unit.
{"title":"Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design","authors":"Shylesh Umapathy, Aaron Stillmaker","doi":"10.1109/PATMOS.2019.8862128","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862128","url":null,"abstract":"With the 54th commemoration of Moores law and the intense development of VLSI technology has permitted more and more IP components to be integrated on a single chip. However, factors such as power consumption has been limiting this growth rate. Low power techniques such as clock gating, power gating, dynamic voltage and frequency scaling, body biasing, and many more have emerged as potential solutions. This paper explores power gating technique and presents the design trade-offs between the ring and grid style of power gate placement in a fine-grained system design. The study used 24 physical designs of 12 different sized MAC units ranging from 44 to 320-bit inputs, and extracted various parameters. The results depict that, using a ring style of placement gives an average increase in IR drop of 9.59% when compared to grid style of placement for 128 to 320-bits input MAC unit. The grid style possesses an additional average congestion of 1.66% when compared to ring style of placement for 192 to 320-bits input MAC unit.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124415928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862162
TaiYu Cheng, Jaehoon Yu, M. Hashimoto
This paper proposes to adopt logarithm-approximate multiplier (LAM) for multiply-accumulate (MAC) computation in neural network (NN) training engine, where LAM approximates a floating-point multiplication as an addition resulting in smaller delay, fewer gates, and lower power consumption. Our implementation of NN training engine for a 2-D classification dataset achieves 10% speed-up and 2.5X and 2.3X efficiency improvement in power and area, respectively. LAM is also highly compatible with conventional bit-width scaling (BWS). When BWS is applied with LAM in four test datasets, more than 5.2X power efficiency improvement is achievable with only 1% accuracy degradation, where 2.3X improvement originates from LAM.
{"title":"Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier","authors":"TaiYu Cheng, Jaehoon Yu, M. Hashimoto","doi":"10.1109/PATMOS.2019.8862162","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862162","url":null,"abstract":"This paper proposes to adopt logarithm-approximate multiplier (LAM) for multiply-accumulate (MAC) computation in neural network (NN) training engine, where LAM approximates a floating-point multiplication as an addition resulting in smaller delay, fewer gates, and lower power consumption. Our implementation of NN training engine for a 2-D classification dataset achieves 10% speed-up and 2.5X and 2.3X efficiency improvement in power and area, respectively. LAM is also highly compatible with conventional bit-width scaling (BWS). When BWS is applied with LAM in four test datasets, more than 5.2X power efficiency improvement is achievable with only 1% accuracy degradation, where 2.3X improvement originates from LAM.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115951598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862049
Amadeo de Gracia Herranz, M. López-Vallejo
The high potential of memristors as multilevel resistance devices. Memristors are promising but suffer from their non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature variations are specially harmful because a small thermal variation changes the operation point of the device in a conclusive way. For these reasons the circuitry required to accurately read or write multilevel devices is complex and area demanding. This paper presents a time-domain architecture based on variable pulses that is able to write different levels in the memristive cell. It is resilient to temperature changes based on an in depth analysis of the definition of the resistance levels. Furthermore, the proposed architecture takes advantage of logarithmic counters to save area. Experimental results show that the proposed approach is valid for a wide temperature range.
{"title":"Temperature-aware writing architecture for multilevel memristive cells","authors":"Amadeo de Gracia Herranz, M. López-Vallejo","doi":"10.1109/PATMOS.2019.8862049","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862049","url":null,"abstract":"The high potential of memristors as multilevel resistance devices. Memristors are promising but suffer from their non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature variations are specially harmful because a small thermal variation changes the operation point of the device in a conclusive way. For these reasons the circuitry required to accurately read or write multilevel devices is complex and area demanding. This paper presents a time-domain architecture based on variable pulses that is able to write different levels in the memristive cell. It is resilient to temperature changes based on an in depth analysis of the definition of the resistance levels. Furthermore, the proposed architecture takes advantage of logarithmic counters to save area. Experimental results show that the proposed approach is valid for a wide temperature range.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122791854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862082
Nikolaos Kefalas, G. Theodoridis
In this paper, an architecture for implementing VESA DSC image compression standard in FPGAs is proposed. DSC uses a very small 3-pixel wide coding unit that restricts the HW architecture of the prediction part to only three pipeline stages. The proposed architecture optimizes the pipeline distribution and performs algorithmic optimizations in order to reduce the critical path inside the prediction modes of DSC. It achieves 62 MHz and requires 18595 slices on Virtex 7 spl. It can process full HD (1920x1080) 4:4:4 images at 30 frames per second and full HD 4:2:2 or 4:2:0 images at 60 frames per second, while it has sub-line latency.
{"title":"Implementing VESA Display Stream Compression Encoder in FPGAs","authors":"Nikolaos Kefalas, G. Theodoridis","doi":"10.1109/PATMOS.2019.8862082","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862082","url":null,"abstract":"In this paper, an architecture for implementing VESA DSC image compression standard in FPGAs is proposed. DSC uses a very small 3-pixel wide coding unit that restricts the HW architecture of the prediction part to only three pipeline stages. The proposed architecture optimizes the pipeline distribution and performs algorithmic optimizations in order to reduce the critical path inside the prediction modes of DSC. It achieves 62 MHz and requires 18595 slices on Virtex 7 spl. It can process full HD (1920x1080) 4:4:4 images at 30 frames per second and full HD 4:2:2 or 4:2:0 images at 60 frames per second, while it has sub-line latency.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122545614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862050
I. Stratakos, Konstantinos Maragos, G. Lentaris
The ever-growing demands for increased speed and low power has led to the development of sophisticated and complex heterogeneous chips consisting of multiple components, such as memories, processors, DSPs, and classical FPGA resources, which operate with diverse specifications. However, their vendor-defined specifications are quite conservative to enable meeting the most demanding application scenarios. Consequently, a surplus of energy consumption is measured in practice. This work focuses on the customization of the operating parameters in SoC-FPGA chips, when executing a HW/SW co-designed application that utilizes multiple of the constituent components of the system. We demonstrate that the nominal application throughput can be attained when multiple components of the SoC are individually fine-tuned to distinct voltage levels, specific to the given application, thus leading to improved energy footprint.
{"title":"Voltage Scaling and Guardband Customization of Multiple Constituent Components in SoC-FPGA","authors":"I. Stratakos, Konstantinos Maragos, G. Lentaris","doi":"10.1109/PATMOS.2019.8862050","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862050","url":null,"abstract":"The ever-growing demands for increased speed and low power has led to the development of sophisticated and complex heterogeneous chips consisting of multiple components, such as memories, processors, DSPs, and classical FPGA resources, which operate with diverse specifications. However, their vendor-defined specifications are quite conservative to enable meeting the most demanding application scenarios. Consequently, a surplus of energy consumption is measured in practice. This work focuses on the customization of the operating parameters in SoC-FPGA chips, when executing a HW/SW co-designed application that utilizes multiple of the constituent components of the system. We demonstrate that the nominal application throughput can be attained when multiple components of the SoC are individually fine-tuned to distinct voltage levels, specific to the given application, thus leading to improved energy footprint.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128261475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/patmos.2019.8862164
{"title":"PATMOS 2019 Author Index","authors":"","doi":"10.1109/patmos.2019.8862164","DOIUrl":"https://doi.org/10.1109/patmos.2019.8862164","url":null,"abstract":"","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127558401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/PATMOS.2019.8862075
Christoph Niemann, Munawar Ali, Jakob Heller, D. Timmermann
Nowadays, VLSI systems suffer from increasing impacts of aging and variability. Traditionally, this is treated by applying extensive guard bands. As those guard bands are chosen at design time, they are necessarily worst case guard bands. Thus, most often they are too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based Adaptive Voltage Scaling (AVS). AVS typically relies on assumptions regarding the timing behavior of the application logic in relation to the behavior of a specific canary or sensor logic. Most published approaches use manually gained empirical data of just a few test chips and application designs for this purpose. However, to practically apply these techniques, an automatic calibration flow is needed. We propose such an automated calibration flow and test it on multiple FPGAs. We achieve an average power saving of 67%.
{"title":"A Calibration Procedure for Sensor Based Adaptive Voltage Scaling Approaches","authors":"Christoph Niemann, Munawar Ali, Jakob Heller, D. Timmermann","doi":"10.1109/PATMOS.2019.8862075","DOIUrl":"https://doi.org/10.1109/PATMOS.2019.8862075","url":null,"abstract":"Nowadays, VLSI systems suffer from increasing impacts of aging and variability. Traditionally, this is treated by applying extensive guard bands. As those guard bands are chosen at design time, they are necessarily worst case guard bands. Thus, most often they are too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based Adaptive Voltage Scaling (AVS). AVS typically relies on assumptions regarding the timing behavior of the application logic in relation to the behavior of a specific canary or sensor logic. Most published approaches use manually gained empirical data of just a few test chips and application designs for this purpose. However, to practically apply these techniques, an automatic calibration flow is needed. We propose such an automated calibration flow and test it on multiple FPGAs. We achieve an average power saving of 67%.","PeriodicalId":430458,"journal":{"name":"2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116370061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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