Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471018
Furkan Ercan, N. Gazala, Howard David
Energy-efficient computing is becoming more important with the latest technology improvements. State-of-the-art dynamic voltage/frequency scaling (DVFS) policies manage resources' voltage and frequency to achieve higher energy efficiency. A DVFS policy manages a single resource by continuously evaluating its utilization. We propose a new integrated DVFS policy that manages both CPU and memory. The policy selects their frequency/voltage based on resources' combined state, rather than evaluating isolated information about each resource. For the SPEC CPU2006 benchmark, results show that our policy has an average of 9.04% energy efficiency improvement for CPU and memory compared to 4.84% savings by an independent policy.
{"title":"An integrated approach to system-level CPU and memory energy efficiency on computing systems","authors":"Furkan Ercan, N. Gazala, Howard David","doi":"10.1109/ICEAC.2012.6471018","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471018","url":null,"abstract":"Energy-efficient computing is becoming more important with the latest technology improvements. State-of-the-art dynamic voltage/frequency scaling (DVFS) policies manage resources' voltage and frequency to achieve higher energy efficiency. A DVFS policy manages a single resource by continuously evaluating its utilization. We propose a new integrated DVFS policy that manages both CPU and memory. The policy selects their frequency/voltage based on resources' combined state, rather than evaluating isolated information about each resource. For the SPEC CPU2006 benchmark, results show that our policy has an average of 9.04% energy efficiency improvement for CPU and memory compared to 4.84% savings by an independent policy.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130250960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471013
Mazen Al Haddad, Zaghloul ElSayed, M. Bayoumi
With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. The power dissipation has become an obsessive concern in the design and implementation of VLSI circuits with the development of the technology. In this paper, conventional low-power design approaches are discussed, and a new design based on Chain structure is presented. It provides a green solution and an alternative way to solve the problems of power supply distribution, interconnection and interfacing in VLSI circuits and a comparison experiment was performed over two circuit layouts of 16bit ALIT implementations and using standard CMOS that saves more than 30% of power consumption, and 0.423 mg of CO2 emission.
{"title":"Green arithmetic logic unit","authors":"Mazen Al Haddad, Zaghloul ElSayed, M. Bayoumi","doi":"10.1109/ICEAC.2012.6471013","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471013","url":null,"abstract":"With the scaling of technology and the need for high performance and more functionality, power dissipation becomes a major bottleneck for microprocessor systems design. The power dissipation has become an obsessive concern in the design and implementation of VLSI circuits with the development of the technology. In this paper, conventional low-power design approaches are discussed, and a new design based on Chain structure is presented. It provides a green solution and an alternative way to solve the problems of power supply distribution, interconnection and interfacing in VLSI circuits and a comparison experiment was performed over two circuit layouts of 16bit ALIT implementations and using standard CMOS that saves more than 30% of power consumption, and 0.423 mg of CO2 emission.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471011
Reha Denker, A. Muhtaroğlu, H. Kulah
Thermoelectric (TE) module integration into a mobile computer has been experimentally investigated in this paper for its energy harvesting opportunities. For this purpose, a detailed Finite Element Analysis (FEA) model was constructed for thermal simulations. The model outputs were then correlated with the thermal validation results of the target system. A suitable “warm spot” has been selected, based on the FEA model, to integrate a commercial TE micro-module inside the system with minimum or no notable impact to the system performance, as measured by thermal changes in the system. The prediction was validated by integrating a TE micro-module to the mobile system under test. Measured TE power generation power density in the carefully selected region of the heat pipe was around 1.26 mW/cm3 with high CPU load and no notable degradation in system performance.
{"title":"Empirical proof of concept for TE generation in mobile computers","authors":"Reha Denker, A. Muhtaroğlu, H. Kulah","doi":"10.1109/ICEAC.2012.6471011","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471011","url":null,"abstract":"Thermoelectric (TE) module integration into a mobile computer has been experimentally investigated in this paper for its energy harvesting opportunities. For this purpose, a detailed Finite Element Analysis (FEA) model was constructed for thermal simulations. The model outputs were then correlated with the thermal validation results of the target system. A suitable “warm spot” has been selected, based on the FEA model, to integrate a commercial TE micro-module inside the system with minimum or no notable impact to the system performance, as measured by thermal changes in the system. The prediction was validated by integrating a TE micro-module to the mobile system under test. Measured TE power generation power density in the carefully selected region of the heat pipe was around 1.26 mW/cm3 with high CPU load and no notable degradation in system performance.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Resolving excessive power dissipation of modern computer systems has become a substantial challenge. However, few research projects have targeted on application power analysis or application-aware power management, which becomes a rising factor in energy efficient system design. In this paper, we describe and implement an application function (subroutine call) level profiler, Safari. It can be used to generate power profiles of each function in an automatic manner. The experiment results using NPB parallel benchmark suite show that Safari is able to collect function level run-time information with overhead (16% on average) comparable to gprof. The power profiling results can be used for code optimization, power-aware scheduling, or even computing resource billing for future research.
{"title":"Safari: Function-level power analysis using automatic instrumentation","authors":"Shinan Wang, Youhuizi Li, Weisong Shi, Lingjun Fan, Abhishek Agrawal","doi":"10.1109/ICEAC.2012.6471014","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471014","url":null,"abstract":"Resolving excessive power dissipation of modern computer systems has become a substantial challenge. However, few research projects have targeted on application power analysis or application-aware power management, which becomes a rising factor in energy efficient system design. In this paper, we describe and implement an application function (subroutine call) level profiler, Safari. It can be used to generate power profiles of each function in an automatic manner. The experiment results using NPB parallel benchmark suite show that Safari is able to collect function level run-time information with overhead (16% on average) comparable to gprof. The power profiling results can be used for code optimization, power-aware scheduling, or even computing resource billing for future research.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115489380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471004
Daniel Schlitt, W. Nebel
Common data center energy efficiency metrics only work on a high abstraction level and require actually measured values. With these metrics, it is not possible to identify the sources of shortcomings in efficiency or to explore possible changes in configuration or architecture, respectively. In this paper, an alternative metric addressing these drawbacks is introduced. The metric makes use of pre-characterized load dependent component models and estimates efficiency for arbitrary input data. The results are objectively comparable between different data center configurations as well as between data center sites, and reasons for inefficiencies may be identified by extracting intermediate results.
{"title":"Load dependent data center energy efficiency metric based on component models","authors":"Daniel Schlitt, W. Nebel","doi":"10.1109/ICEAC.2012.6471004","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471004","url":null,"abstract":"Common data center energy efficiency metrics only work on a high abstraction level and require actually measured values. With these metrics, it is not possible to identify the sources of shortcomings in efficiency or to explore possible changes in configuration or architecture, respectively. In this paper, an alternative metric addressing these drawbacks is introduced. The metric makes use of pre-characterized load dependent component models and estimates efficiency for arbitrary input data. The results are objectively comparable between different data center configurations as well as between data center sites, and reasons for inefficiencies may be identified by extracting intermediate results.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126795237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471026
Didem Gürdür, A. Muhtaroğlu
Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array multiplier architectures, which are most commonly used in such applications. Gate level library design parameters are utilized to derive energy-delay performance for any given set of input vector patterns, and multiplier size. Vector and size dependent factors are therefore clearly identified. Examples are provided from carry save array multiplier (CSAM) and ripple carry array multiplier (RCAM) to demonstrate the capabilities for the tool.
{"title":"PETAM: Power estimation tool for array multipliers","authors":"Didem Gürdür, A. Muhtaroğlu","doi":"10.1109/ICEAC.2012.6471026","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471026","url":null,"abstract":"Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array multiplier architectures, which are most commonly used in such applications. Gate level library design parameters are utilized to derive energy-delay performance for any given set of input vector patterns, and multiplier size. Vector and size dependent factors are therefore clearly identified. Examples are provided from carry save array multiplier (CSAM) and ripple carry array multiplier (RCAM) to demonstrate the capabilities for the tool.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471027
Melissa Stockman, M. Awad, Haitham Akkary, R. Khanna
Because knowing information about the currently running workload and the thermal status of the processor is of importance for more adequate planning and allocating resources in microprocessor environments, we propose in this paper using support vector regression (SVR) to predict future processor thermal status as well as the currently running workload. We build two generalized SVR models trained with data from monitoring hardware performance counters collected from running SPEC2006 benchmarks. The first model predicts the Central Processing Unit's thermal status in Celsius with a percentage error of less than 10%. The second model predicts the current workload with a percentage error of 0.08% for a heterogeneous training set of 6 different integer and floating point benchmark workloads. Cross validation for the two models show the effectiveness of our approach and motivate follow on research.
{"title":"Thermal status and workload prediction using support vector regression","authors":"Melissa Stockman, M. Awad, Haitham Akkary, R. Khanna","doi":"10.1109/ICEAC.2012.6471027","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471027","url":null,"abstract":"Because knowing information about the currently running workload and the thermal status of the processor is of importance for more adequate planning and allocating resources in microprocessor environments, we propose in this paper using support vector regression (SVR) to predict future processor thermal status as well as the currently running workload. We build two generalized SVR models trained with data from monitoring hardware performance counters collected from running SPEC2006 benchmarks. The first model predicts the Central Processing Unit's thermal status in Celsius with a percentage error of less than 10%. The second model predicts the current workload with a percentage error of 0.08% for a heterogeneous training set of 6 different integer and floating point benchmark workloads. Cross validation for the two models show the effectiveness of our approach and motivate follow on research.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125225900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471002
Mohamed W. El Mahalawy, Y. Ismail
Resonant clocking is a promising low power alternative for conventional clocking method. In this work, a design methodology is presented for square wave resonant clocking technique to assure minimum power consumption. These equations were verified by designing a differential clock generator which showed 55% power savings compared to conventional clocking.
{"title":"Design methodology for square wave resonant clock generators","authors":"Mohamed W. El Mahalawy, Y. Ismail","doi":"10.1109/ICEAC.2012.6471002","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471002","url":null,"abstract":"Resonant clocking is a promising low power alternative for conventional clocking method. In this work, a design methodology is presented for square wave resonant clocking technique to assure minimum power consumption. These equations were verified by designing a differential clock generator which showed 55% power savings compared to conventional clocking.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128168310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471021
A. Helmy, Alaa R. Alameldeen
We present a detailed analysis of the bandwidth requirements in a network-on-chip at high and low voltages. We propose mechanisms to maintain the functionality of a system-on-chip despite the presence of failures in the network-on-chip used to connect its components. Our mechanisms alleviate failures in the links and/or the connected buffers, and allow voltage scaling for the network. Our best mechanism allows reliable network operation well below 500 mV while reducing power by more than a factor of 5 and energy by 28% compared to a baseline without fault-tolerance mechanisms.
{"title":"Redundancy and ECC mechanisms to improve energy efficiency of on-die interconnects","authors":"A. Helmy, Alaa R. Alameldeen","doi":"10.1109/ICEAC.2012.6471021","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471021","url":null,"abstract":"We present a detailed analysis of the bandwidth requirements in a network-on-chip at high and low voltages. We propose mechanisms to maintain the functionality of a system-on-chip despite the presence of failures in the network-on-chip used to connect its components. Our mechanisms alleviate failures in the links and/or the connected buffers, and allow voltage scaling for the network. Our best mechanism allows reliable network operation well below 500 mV while reducing power by more than a factor of 5 and energy by 28% compared to a baseline without fault-tolerance mechanisms.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114497887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-12-01DOI: 10.1109/ICEAC.2012.6471019
Grace Metri, Abhishek Agrawal, Sherine Abdelhak
Technology clients expect with the release of a new device model that the device is more powerful and more energy efficient than its predecessor. There are many profiling tools aimed at profiling the energy efficiency of different platforms in order to provide consumers fair comparison of the energy efficiency of available platforms. Since improving the power consumption of devices is no longer the sole duty of hardware manufacturers but it is also the responsibility of software developers, we present a case study in this paper where we power profile Windows® 8 and Windows® 7 on the same hardware configuration using MobileMark® 2012 in order to compare how their efficiency compare to one another. Based on our results, we were able to show that Windows® 8 is a step forward to a better energy efficient operating system when compared to its predecessor.
{"title":"Power profiling with real-world workloads: A case study with MobileMark 2012","authors":"Grace Metri, Abhishek Agrawal, Sherine Abdelhak","doi":"10.1109/ICEAC.2012.6471019","DOIUrl":"https://doi.org/10.1109/ICEAC.2012.6471019","url":null,"abstract":"Technology clients expect with the release of a new device model that the device is more powerful and more energy efficient than its predecessor. There are many profiling tools aimed at profiling the energy efficiency of different platforms in order to provide consumers fair comparison of the energy efficiency of available platforms. Since improving the power consumption of devices is no longer the sole duty of hardware manufacturers but it is also the responsibility of software developers, we present a case study in this paper where we power profile Windows® 8 and Windows® 7 on the same hardware configuration using MobileMark® 2012 in order to compare how their efficiency compare to one another. Based on our results, we were able to show that Windows® 8 is a step forward to a better energy efficient operating system when compared to its predecessor.","PeriodicalId":436221,"journal":{"name":"2012 International Conference on Energy Aware Computing","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134269420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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