In order to fulfill the increasing performance requirements, complex embedded systems design makes use of many processors communicating through efficient infrastructures, performing multiprocessor-systems-on-chip (MPSoCs). Issues related to execution time and energy consumption estimations become more relevant during the design stage of such systems, in order to verify their compliance with the specification. Different estimation techniques have been proposed, including analytical and simulation-based methods. Analytical methods are faster than simulation-based methods, but the system description is more complex, and sometimes this approach conducts to low precision results misleading future design steps. On the other hand, the more accurate results achieved with simulation-based method, using low-level descriptions, may delay the design making it unfeasible or at least affecting the time-to-market. In this context, improvements in simulation-based methods become pertinent. This paper presents a study, a design flow and a tool for high-level simulation-based estimation of execution time and energy consumption of homogeneous MPSoCs. The implemented tool, which employs the methodology presented in this paper, improved dramatically simulation times when compared to RTL simulations. The preliminary results show that, for some cases, the RTL simulation takes tens hours while the implemented tool gets close estimation results in just few seconds.
{"title":"High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping","authors":"S. J. Filho, A. Aguiar, C. Marcon, Fabiano Hessel","doi":"10.1109/RSP.2008.25","DOIUrl":"https://doi.org/10.1109/RSP.2008.25","url":null,"abstract":"In order to fulfill the increasing performance requirements, complex embedded systems design makes use of many processors communicating through efficient infrastructures, performing multiprocessor-systems-on-chip (MPSoCs). Issues related to execution time and energy consumption estimations become more relevant during the design stage of such systems, in order to verify their compliance with the specification. Different estimation techniques have been proposed, including analytical and simulation-based methods. Analytical methods are faster than simulation-based methods, but the system description is more complex, and sometimes this approach conducts to low precision results misleading future design steps. On the other hand, the more accurate results achieved with simulation-based method, using low-level descriptions, may delay the design making it unfeasible or at least affecting the time-to-market. In this context, improvements in simulation-based methods become pertinent. This paper presents a study, a design flow and a tool for high-level simulation-based estimation of execution time and energy consumption of homogeneous MPSoCs. The implemented tool, which employs the methodology presented in this paper, improved dramatically simulation times when compared to RTL simulations. The preliminary results show that, for some cases, the RTL simulation takes tens hours while the implemented tool gets close estimation results in just few seconds.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123520533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Complex image processing algorithms, when implemented on chip, require a significant amount of memory. Communication between the processing elements of an image processing system consumes most of the bandwidth of the system bus. This paper presents a novel architecture for a system on chip targeting image processing applications. Main focus is placed on optimizing the communication overhead between the image processing elements. Evaluation of this architecture is made in a custom FPGA platform and in ASIC implementation.
{"title":"A Novel System-on-Chip Architecture for Efficient Image Processing","authors":"V. Mariatos, K. Adaos, G. Alexiou","doi":"10.1109/RSP.2008.33","DOIUrl":"https://doi.org/10.1109/RSP.2008.33","url":null,"abstract":"Complex image processing algorithms, when implemented on chip, require a significant amount of memory. Communication between the processing elements of an image processing system consumes most of the bandwidth of the system bus. This paper presents a novel architecture for a system on chip targeting image processing applications. Main focus is placed on optimizing the communication overhead between the image processing elements. Evaluation of this architecture is made in a custom FPGA platform and in ASIC implementation.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125697304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a coverage-driven Constraint random-based functional verification method of memory controller in a microprocessor. Many special functions are integrated into this memory controller for anti-radiating, so it is more difficult to verify . This system of verification, which is creating by means of verification methodology manual (VMM) for systemverilog and classification trees, is reusable, scalable, configurable and can reduce time of verification.
{"title":"A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller","authors":"Yingpan Wu, Lixin Yu, Lidong Lan, Haiyang Zhou","doi":"10.1109/RSP.2008.12","DOIUrl":"https://doi.org/10.1109/RSP.2008.12","url":null,"abstract":"This paper presents a coverage-driven Constraint random-based functional verification method of memory controller in a microprocessor. Many special functions are integrated into this memory controller for anti-radiating, so it is more difficult to verify . This system of verification, which is creating by means of verification methodology manual (VMM) for systemverilog and classification trees, is reusable, scalable, configurable and can reduce time of verification.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133189741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an application-specific instruction set processor (ASIP) -controlled inverse integer transform IP block on a system-on-chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4times4 and 8times8 inverse integer transform with additional support for 2times2 and 4times4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4times4 circuit in the 8times8 circuit, while achieving a speed of 176 MHz.
{"title":"ASIP-controlled Inverse Integer Transform for H.264/AVC Compression","authors":"N. Ngo, T. Do, T. M. Le, Y. S. Kadam, A. Bermak","doi":"10.1109/RSP.2008.34","DOIUrl":"https://doi.org/10.1109/RSP.2008.34","url":null,"abstract":"In this paper, an application-specific instruction set processor (ASIP) -controlled inverse integer transform IP block on a system-on-chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4times4 and 8times8 inverse integer transform with additional support for 2times2 and 4times4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4times4 circuit in the 8times8 circuit, while achieving a speed of 176 MHz.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132283727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
André Meisel, Alexander Draeger, Sven Schneider, W. Hardt
Reconfigurable hardware combines the flexibility of software and the efficiency of hardware. Thus, embedded systems can benefit from reconfiguration techniques. Many special aspects of dynamic and partial reconfiguration have been already analyzed. On the one hand reconfiguration is mostly used like a hot-plug mechanism. On the other hand approaches similar to the overlaying technique, known from the Pascal runtime library, can be used. The overlaying algorithm schedules different functions to the same hardware resource during runtime. In this paper, the overlaying concept is adapted to reconfiguration. The used reconfiguration model is presented and the costs are optimized and evaluated. The average reconfiguration time is minimized. These methods have been integrated into the design flow for reconfiguration. This approach is best suited for small FPGAs, which are crucial in embedded system design.
{"title":"Design Flow for Reconfiguration Based on the Overlaying Concept","authors":"André Meisel, Alexander Draeger, Sven Schneider, W. Hardt","doi":"10.1109/RSP.2008.20","DOIUrl":"https://doi.org/10.1109/RSP.2008.20","url":null,"abstract":"Reconfigurable hardware combines the flexibility of software and the efficiency of hardware. Thus, embedded systems can benefit from reconfiguration techniques. Many special aspects of dynamic and partial reconfiguration have been already analyzed. On the one hand reconfiguration is mostly used like a hot-plug mechanism. On the other hand approaches similar to the overlaying technique, known from the Pascal runtime library, can be used. The overlaying algorithm schedules different functions to the same hardware resource during runtime. In this paper, the overlaying concept is adapted to reconfiguration. The used reconfiguration model is presented and the costs are optimized and evaluated. The average reconfiguration time is minimized. These methods have been integrated into the design flow for reconfiguration. This approach is best suited for small FPGAs, which are crucial in embedded system design.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114920540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the biggest challenges in the software industry is to ensure that a software product meets all user specifications. In this paper, we propose to establish traceability of functional requirements expressed in a SRS document among different UML diagrams that are used in requirement analysis and design phases. We have used Z notation as the formal language for representing the SRS and design artifacts and this formal notation is used to automatically establish trace paths based on certain rules. We present an implementation methodology based on XML for development of a prototype. A snapshot of some of the results based on a case study has been shown for illustration of our approach. Our approach will help in identifying missing requirements or incomplete requirement coverage as well highlight the impact points for effective change management of requirements.
{"title":"Requirement Traceability in Software Development Process: An Empirical Approach","authors":"S. Sengupta, A. Kanjilal, S. Bhattacharya","doi":"10.1109/RSP.2008.14","DOIUrl":"https://doi.org/10.1109/RSP.2008.14","url":null,"abstract":"One of the biggest challenges in the software industry is to ensure that a software product meets all user specifications. In this paper, we propose to establish traceability of functional requirements expressed in a SRS document among different UML diagrams that are used in requirement analysis and design phases. We have used Z notation as the formal language for representing the SRS and design artifacts and this formal notation is used to automatically establish trace paths based on certain rules. We present an implementation methodology based on XML for development of a prototype. A snapshot of some of the results based on a case study has been shown for illustration of our approach. Our approach will help in identifying missing requirements or incomplete requirement coverage as well highlight the impact points for effective change management of requirements.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132740235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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