This paper presents an efficient run-time hardware/software scheduling approach. This scheduling heuristic consists in mapping on-line the different tasks of a highly dynamic application in such a way that the total execution time is minimized.Our approach takes advantage of the reconfiguration property of the considered architecture to adapt processing to the system dynamics. We compare our heuristic with another similar approach. We present the results of our scheduling method on an image processing application. Our experiments include simulation and synthesis results on a Virtex2P based platform. This results show a better performance against existing methods.
{"title":"Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip","authors":"Ghaffari Fakhreddine, Benoît Miramond, F. Verdier","doi":"10.1109/RSP.2008.28","DOIUrl":"https://doi.org/10.1109/RSP.2008.28","url":null,"abstract":"This paper presents an efficient run-time hardware/software scheduling approach. This scheduling heuristic consists in mapping on-line the different tasks of a highly dynamic application in such a way that the total execution time is minimized.Our approach takes advantage of the reconfiguration property of the considered architecture to adapt processing to the system dynamics. We compare our heuristic with another similar approach. We present the results of our scheduling method on an image processing application. Our experiments include simulation and synthesis results on a Virtex2P based platform. This results show a better performance against existing methods.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126556060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Laurent Moss, Marc-André Cantin, G. Bois, E. Aboulhamid
Traditional register-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin- and cycle-accurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.
{"title":"Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology","authors":"Laurent Moss, Marc-André Cantin, G. Bois, E. Aboulhamid","doi":"10.1109/RSP.2008.17","DOIUrl":"https://doi.org/10.1109/RSP.2008.17","url":null,"abstract":"Traditional register-transfer level design methodologies for systems-on-chip are failing to keep up with the growing complexity of embedded applications and architectures. A well-known solution is to raise the level of design abstraction by using system-level methodologies. The refinement from system-level specifications to concrete implementations is an essential step in a system-level design methodology. This article presents a novel methodology for the refinement from transaction-level communications to pin- and cycle-accurate protocols as well as the generation of synthesizable hardware from system-level specifications. Automatic communication refinement and hardware synthesis were successfully applied to a rover guiding system. Hand-coded and automatically generated register-transfer level modules of the rover are compared. Results show that a hardware/software implementation of the guiding system using generated register-transfer level modules has overheads of less than one percent in latency and hardware area when compared to an implementation using hand-coded modules.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130755292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The widespread availability of field programmable gate arrays (FPGA) coupled with different implementations of "soft-core" processors has created a need to find new methods for optimizing these processors. Because design space is limited on most FPGA's and the maximum clock rate of these processors is heavily bound to the overall size and resource usage it is necessary to find ways to minimize the size of the processor. One such way to minimize the size of a "soft-core" processor is to customize the instruction set on which it operates. Removing instructions that are supported but not utilized by target applications may provide a reduction in design space usage as well as an increase in maximum clock frequencies for the processor.
{"title":"Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine","authors":"R. Wood, J. Libby, K. Kent","doi":"10.1109/RSP.2008.10","DOIUrl":"https://doi.org/10.1109/RSP.2008.10","url":null,"abstract":"The widespread availability of field programmable gate arrays (FPGA) coupled with different implementations of \"soft-core\" processors has created a need to find new methods for optimizing these processors. Because design space is limited on most FPGA's and the maximum clock rate of these processors is heavily bound to the overall size and resource usage it is necessary to find ways to minimize the size of the processor. One such way to minimize the size of a \"soft-core\" processor is to customize the instruction set on which it operates. Removing instructions that are supported but not utilized by target applications may provide a reduction in design space usage as well as an increase in maximum clock frequencies for the processor.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125648363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a re-configurable sensor node prototype platform, and an auxiliary network structure for granting a reliable communication channel for runtime debugging without interfering with the primary radio link. For the prototype platform, we propose a modular design which incorporates a single FPGA with high gate count as core of the platform. The FPGA is utilized to emulate arbitrary mote architectures and realize flexible interfaces to sensors and radio transceivers. As a major benefit, versatile debugging interfaces can additionally be implemented in the same FPGA, seamlessly integrating into the emulated mote architecture, with direct access to internal information. This easily allows to realize passive system monitors as well as active debugging control. By using a deployment support network to exchange relevant information, all motes can be monitored and controlled simultaneously by a user. The paper presents the proposed methodology, its implementation, and a practical application example in detail.
{"title":"A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support","authors":"H. Hinkelmann, A. Reinhardt, M. Glesner","doi":"10.1109/RSP.2008.13","DOIUrl":"https://doi.org/10.1109/RSP.2008.13","url":null,"abstract":"In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a re-configurable sensor node prototype platform, and an auxiliary network structure for granting a reliable communication channel for runtime debugging without interfering with the primary radio link. For the prototype platform, we propose a modular design which incorporates a single FPGA with high gate count as core of the platform. The FPGA is utilized to emulate arbitrary mote architectures and realize flexible interfaces to sensors and radio transceivers. As a major benefit, versatile debugging interfaces can additionally be implemented in the same FPGA, seamlessly integrating into the emulated mote architecture, with direct access to internal information. This easily allows to realize passive system monitors as well as active debugging control. By using a deployment support network to exchange relevant information, all motes can be monitored and controlled simultaneously by a user. The paper presents the proposed methodology, its implementation, and a practical application example in detail.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114469376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Glas, Alexander Klimm, David Schwab, K. Müller-Glaser, J. Becker
Abstract This contribution proposes a secure and efficient method for updating reconfigurable hardware devices like FPGAs by using trusted computing technology. An interesting application is latent in the domain of embedded systems like in the automotive sector when durable products shall be updated in the field while stringent safety and security constraints have to be met. We propose an architecture to send arbitrary FPGA configuration bitstreams personalized to specific platforms over public channels. By using trusted platform modules we achieve a secure delivery chain for IP cores without the need of predefined shared secrets or keys. Furthermore integrity and confidentiality of the IP and enforcement of usage policies can be guaranteed. This enables the vendor to ensure a correct configuration of the device in order to adhere safety commitments. As a side effect such methods can also be used to deliver IP-cores from multiple IP vendors to remote devices securely and efficiently.
{"title":"A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates","authors":"B. Glas, Alexander Klimm, David Schwab, K. Müller-Glaser, J. Becker","doi":"10.1109/RSP.2008.24","DOIUrl":"https://doi.org/10.1109/RSP.2008.24","url":null,"abstract":"Abstract This contribution proposes a secure and efficient method for updating reconfigurable hardware devices like FPGAs by using trusted computing technology. An interesting application is latent in the domain of embedded systems like in the automotive sector when durable products shall be updated in the field while stringent safety and security constraints have to be met. We propose an architecture to send arbitrary FPGA configuration bitstreams personalized to specific platforms over public channels. By using trusted platform modules we achieve a secure delivery chain for IP cores without the need of predefined shared secrets or keys. Furthermore integrity and confidentiality of the IP and enforcement of usage policies can be guaranteed. This enables the vendor to ensure a correct configuration of the device in order to adhere safety commitments. As a side effect such methods can also be used to deliver IP-cores from multiple IP vendors to remote devices securely and efficiently.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124644640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The complexity of multi-processor system-on-chip (MPSOC) design has made design, simulation and verification/validation a significant challenge for SOC designers. To produce a complex MPSOC system in a short design cycle, system simulation and validation must be done in an affordable time. Solutions to this challenge include moving simulation to a higher abstraction level such as in SystemC, and validating the system through FPGA prototyping. This paper presents a MPSOC system which consists of 4 Xilinx microblaze processors interconnected with FSL (fast simplex link) channels. This system has two equivalent "views": one is a high-level SystemC framework for modeling and simulation, and the other is a hardware framework for FPGA implementation and prototyping. This system is supplied to the member universities of the Canadian System-on-Chip Research Network (SOCRN), managed by CMC Microsystems, as an MPSOC design, simulation and validation environment.
{"title":"A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping","authors":"S. Xu, H. Pollitt-Smith","doi":"10.1109/RSP.2008.15","DOIUrl":"https://doi.org/10.1109/RSP.2008.15","url":null,"abstract":"The complexity of multi-processor system-on-chip (MPSOC) design has made design, simulation and verification/validation a significant challenge for SOC designers. To produce a complex MPSOC system in a short design cycle, system simulation and validation must be done in an affordable time. Solutions to this challenge include moving simulation to a higher abstraction level such as in SystemC, and validating the system through FPGA prototyping. This paper presents a MPSOC system which consists of 4 Xilinx microblaze processors interconnected with FSL (fast simplex link) channels. This system has two equivalent \"views\": one is a high-level SystemC framework for modeling and simulation, and the other is a hardware framework for FPGA implementation and prototyping. This system is supplied to the member universities of the Canadian System-on-Chip Research Network (SOCRN), managed by CMC Microsystems, as an MPSOC design, simulation and validation environment.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127260870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Network intrusion detection system (NIDS) demands have been steadily increasing over the past few years. Current solutions using software become inefficient running on high speed high volume networks and will end up dropping packets. Hardware solutions are available and result in much higher efficiency but present problems such as flexibility and cost. Our proposed system uses a modified version of Snort, a robust widely deployed open-sourced NIDS. Snort spends a significant fraction of its processing time doing pattern matching. Our proposed system runs Snort in software until it gets to the pattern matching function and then off loads that processing to the field programmable gate array (FPGA). The hardware is able to process data at up to 1.7 GB/s on one Xilinx XC2VP100 FPGA. Our system is more flexible than other FPGA string matching designs in that the rules are not hard-coded. The design is scalable and allows FPGAs to be used in parallel to increase the processing speed even further.
{"title":"Flexible Software-Hardware Network Intrusion Detection System","authors":"Ryan B. Proudfoot, K. Kent, E. Aubanel, Nan Chen","doi":"10.1109/RSP.2008.11","DOIUrl":"https://doi.org/10.1109/RSP.2008.11","url":null,"abstract":"Network intrusion detection system (NIDS) demands have been steadily increasing over the past few years. Current solutions using software become inefficient running on high speed high volume networks and will end up dropping packets. Hardware solutions are available and result in much higher efficiency but present problems such as flexibility and cost. Our proposed system uses a modified version of Snort, a robust widely deployed open-sourced NIDS. Snort spends a significant fraction of its processing time doing pattern matching. Our proposed system runs Snort in software until it gets to the pattern matching function and then off loads that processing to the field programmable gate array (FPGA). The hardware is able to process data at up to 1.7 GB/s on one Xilinx XC2VP100 FPGA. Our system is more flexible than other FPGA string matching designs in that the rules are not hard-coded. The design is scalable and allows FPGAs to be used in parallel to increase the processing speed even further.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115900340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Senouci, Abdellah-Medjadji Kouadri-Kouadri, F. Rousseau, F. Pétrot
Heterogeneous multiprocessor systems on-chip (MPSoC) are considered to be the next generation of multiprocessor architectures able to deal with the ever increasing performances and scalability demands. In fact, combining heterogeneous processors in the same architecture allows drawing on strength from each kind of processor, increasing overall system performance and efficiency. However, such a design introduces new challenges, especially for embedded software designers. Multi-CPU/FPGA platform based prototyping approach is an attractive solution for fast validation of MPSoC's embedded software. We address in this paper, the difficulty of ensuring an efficient bridging between processors in heterogeneous MPSoC. We propose a common FPGA based middleware structure to manage communication and synchronisation between the processors. Then, we describe a semi-systematic design space exploration framework for automatic inter- processor communication and synchronization refinement.
{"title":"Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers","authors":"B. Senouci, Abdellah-Medjadji Kouadri-Kouadri, F. Rousseau, F. Pétrot","doi":"10.1109/RSP.2008.27","DOIUrl":"https://doi.org/10.1109/RSP.2008.27","url":null,"abstract":"Heterogeneous multiprocessor systems on-chip (MPSoC) are considered to be the next generation of multiprocessor architectures able to deal with the ever increasing performances and scalability demands. In fact, combining heterogeneous processors in the same architecture allows drawing on strength from each kind of processor, increasing overall system performance and efficiency. However, such a design introduces new challenges, especially for embedded software designers. Multi-CPU/FPGA platform based prototyping approach is an attractive solution for fast validation of MPSoC's embedded software. We address in this paper, the difficulty of ensuring an efficient bridging between processors in heterogeneous MPSoC. We propose a common FPGA based middleware structure to manage communication and synchronisation between the processors. Then, we describe a semi-systematic design space exploration framework for automatic inter- processor communication and synchronization refinement.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"77 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The reliability requirements for space-critical system call for specific tools and models. Space systems have been a long time user of models (synchronous or asynchronous building blocks), from which code generators could derive analyzable code, while also providing additional benefits like simulation, model checking, etc. However, the integration of multiple models to form one complete system was done manually, in an ad hoc and time consuming way. In this paper, we show how a MDE process built around ASN.l, SDL, SCADE and AADL allows for more rigor by separating concerns to defining data models, functional blocks, interfaces and then behavior of a complete system; and then weave them to build the final systems. By automating the full process, we show the benefits from the system designer perspective: reduced implied complexity, quicker access to evaluation prototype of the end system.
{"title":"Using MDE for the Rapid Prototyping of Space Critical Systems","authors":"J. Hugues, M. Perrotin, T. Tsiodras","doi":"10.1109/RSP.2008.19","DOIUrl":"https://doi.org/10.1109/RSP.2008.19","url":null,"abstract":"The reliability requirements for space-critical system call for specific tools and models. Space systems have been a long time user of models (synchronous or asynchronous building blocks), from which code generators could derive analyzable code, while also providing additional benefits like simulation, model checking, etc. However, the integration of multiple models to form one complete system was done manually, in an ad hoc and time consuming way. In this paper, we show how a MDE process built around ASN.l, SDL, SCADE and AADL allows for more rigor by separating concerns to defining data models, functional blocks, interfaces and then behavior of a complete system; and then weave them to build the final systems. By automating the full process, we show the benefits from the system designer perspective: reduced implied complexity, quicker access to evaluation prototype of the end system.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125482606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Configurable processors are adopted by several latest embedded system projects to make use of application specific custom instructions for instruction level parallelism. Meanwhile, designers also use multiple processors for thread level parallelism. Configurable heterogeneous multi-processor system-on-chip (CH-MPSoC) has both parallelism advantages and seems to be a good solution for future embedded systems. Because CH-MPSoC has lots of architectural parameters, new design methodologies are required to help exploring this huge design space and finding a suitable solution for all user-defined constraints. We propose a new exploration flow using a budget based problem partitioning approach integrated with multiple abstraction levels. By using several abstraction levels, global budgets of speed, power and cost can be decomposed into detailed ones which are mapped onto each component. One special abstraction level called transaction accurate level is used in our flow to model both multi-processor architectures and configurable processors. At this level, hardware tasks and peripherals use transaction level modeling to achieve high simulation speed. Statistic information of configurable processors is abstracted and annotated to each software tasks. The execution results are used to adjust budgets and guide automatic extended instructions generation. With the Motion-JPEG case study, we illustrate detailed advantages of our CH-MPSoC exploration flow.
{"title":"Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels","authors":"Hao Shen, P. Gerin, F. Pétrot","doi":"10.1109/RSP.2008.18","DOIUrl":"https://doi.org/10.1109/RSP.2008.18","url":null,"abstract":"Configurable processors are adopted by several latest embedded system projects to make use of application specific custom instructions for instruction level parallelism. Meanwhile, designers also use multiple processors for thread level parallelism. Configurable heterogeneous multi-processor system-on-chip (CH-MPSoC) has both parallelism advantages and seems to be a good solution for future embedded systems. Because CH-MPSoC has lots of architectural parameters, new design methodologies are required to help exploring this huge design space and finding a suitable solution for all user-defined constraints. We propose a new exploration flow using a budget based problem partitioning approach integrated with multiple abstraction levels. By using several abstraction levels, global budgets of speed, power and cost can be decomposed into detailed ones which are mapped onto each component. One special abstraction level called transaction accurate level is used in our flow to model both multi-processor architectures and configurable processors. At this level, hardware tasks and peripherals use transaction level modeling to achieve high simulation speed. Statistic information of configurable processors is abstracted and annotated to each software tasks. The execution results are used to adjust budgets and guide automatic extended instructions generation. With the Motion-JPEG case study, we illustrate detailed advantages of our CH-MPSoC exploration flow.","PeriodicalId":436363,"journal":{"name":"2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130190563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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