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2008 International Symposium on Industrial Embedded Systems最新文献

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Dynamic voltage and frequency scaling for optimal real-time scheduling on multiprocessors 多处理器上最优实时调度的动态电压和频率缩放
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577677
Kenji Funaoka, Akira Takeda, S. Kato, N. Yamasaki
Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulability improvement but also energy efficiency for the systems. In this paper, real-time dynamic voltage and frequency scaling (RT DVFS) techniques based on the theoretically optimal real-time static voltage and frequency scaling (RTSVFS) techniques proposed in our previous work are presented for multiprocessor systems. Simulation results show that RT-DVFS covers up the disadvantages of RT-SVFS in the sense that RTDVFS are not practically affected by the difference among systems, whereas the energy consumption of RT-SVFS highly depends on the selectable processor frequency especially in high system utilization.
对于嵌入式系统来说,不仅系统性能重要,能源效率也至关重要。优化实时调度不仅能提高系统的可调度性,还能提高系统的能效。本文在前人提出的理论上最优的实时静态电压和频率缩放(RTSVFS)技术的基础上,提出了用于多处理器系统的实时动态电压和频率缩放(RT DVFS)技术。仿真结果表明,RT-DVFS克服了RT-SVFS的缺点,不受系统间差异的影响,但在系统利用率较高的情况下,RT-SVFS的能量消耗很大程度上取决于可选择的处理器频率。
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引用次数: 25
Implementation of an efficient RDMA mechanism tightly coupled with a TCP/IP offload engine 实现了与TCP/IP卸载引擎紧密耦合的高效RDMA机制
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577684
Hankook Jang, Sang-Hwa Chung, Dae-Hyun Yoo
We develop a hybrid TCP/IP offload engine (hybrid TOE) that processes TCP/IP via hardware/software coprocessing based on an FPGA and a general-purpose embedded processor. We also develop an efficient remote direct memory access (RDMA) mechanism that is tightly coupled with the hybrid TOE. In this mechanism, the hybrid TOE performs CRC calculations using hardware modules and supports zero-copy data transmission; the host CPU simply generates and processes RDMA protocol headers. By using the hybrid TOE and the RDMA mechanism, computer systems can achieve good network performance with very low CPU utilizations, and thus they can be expected to show a great improvement in overall performance. In experiments on a gigabit Ethernet network, although the embedded processor operated with a 300 MHz core clock, which was one-seventh the speed of the host CPUpsilas clock, the hybrid TOE showed a minimum latency of 17.4 mus and a maximum bandwidth of 736 Mbps. The RDMA mechanism exhibited a minimum latency of 20.6 mus and a maximum bandwidth of 642 Mbps. Most importantly, the hybrid TOE and the TOE-based RDMA mechanism gave CPU utilizations of less than 5.6% and 8.4%, respectively-approximately one-tenth the utilizations when TCP/IP and TCP/IP-based RDMA were processed by the host CPU.
我们开发了一种混合TCP/IP卸载引擎(hybrid TOE),该引擎基于FPGA和通用嵌入式处理器,通过硬件/软件协同处理TCP/IP。我们还开发了一种与混合TOE紧密耦合的高效远程直接内存访问(RDMA)机制。在该机制中,混合TOE使用硬件模块进行CRC计算,支持零拷贝数据传输;主机CPU只是生成和处理RDMA协议头。通过使用混合TOE和RDMA机制,计算机系统可以在非常低的CPU利用率下获得良好的网络性能,从而可以预期在整体性能上有很大的提高。在千兆以太网网络上的实验中,尽管嵌入式处理器以300 MHz的核心时钟运行,这是主机cpu时钟速度的七分之一,但混合TOE的最小延迟为17.4 mus,最大带宽为736 Mbps。RDMA机制的最小延迟为20.6 mus,最大带宽为642 Mbps。最重要的是,混合TOE和基于TOE的RDMA机制的CPU利用率分别低于5.6%和8.4%——大约是由主机CPU处理TCP/IP和基于TCP/IP的RDMA时的十分之一。
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引用次数: 6
Validation of executable application models mapped onto network-on-chip platforms 验证映射到片上网络平台上的可执行应用程序模型
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577689
Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes
Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.
由于当今嵌入式系统的设计尺寸、复杂性和异构性不断增加,设计人员需要新颖的设计方法来验证特定于应用程序的功能以及不同的平台实现方案。理想情况下,这应该发生在设计过程的早期阶段,这样设计师就可以在他们不得不提交特定的处理器架构或定制硬件实现之前探索设计空间。本文利用分层设计风格和面向参与者框架对异构计算模型(MoC)的支持,提出了一种多处理器嵌入式系统建模和验证的方法。所提出的方法是完全基于模型的,对应用程序和底层实现平台具有不同的建模风格。在本文中,我们重点关注使用托勒密II参与者和UML序列图建模的应用程序的验证,并将其映射到多处理器片上网络(NoC)平台上。我们还提供了一个案例研究,其中一个可执行应用程序模型被映射到不同的NoC拓扑,并显示了每个备选方案的通信延迟的仿真结果。
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引用次数: 14
Scalably distributed SystemC simulation for embedded applications 嵌入式应用的可扩展分布式SystemC仿真
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577715
Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, L. Thiele
SystemC becomes popular as an efficient system-level modelling language and simulation platform. However, the sole-thread simulation kernel obstacles its performance progress from the potential of modern multi-core machines. This is further aggravated by modern embedded applications that are getting more complex. In this paper, we propose a technique which supports the geographical distribution of an arbitrary number of SystemC simulations, without modifying the SystemC simulation kernel. This technique is suited to distribute functional and approximated-timed TLM simulation. We integrate this technique into a complete MPSoC design space exploration framework and the improvement gained is promising.
作为一种高效的系统级建模语言和仿真平台,SystemC越来越受欢迎。然而,单线程仿真内核阻碍了其性能的进步,使其无法发挥现代多核机器的潜力。现代嵌入式应用程序变得越来越复杂,这进一步加剧了这种情况。在本文中,我们提出了一种技术,该技术在不修改SystemC仿真内核的情况下支持任意数量的SystemC仿真的地理分布。该技术适用于分布函数和近似时间的TLM仿真。我们将该技术集成到一个完整的MPSoC设计空间探索框架中,所获得的改进是有希望的。
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引用次数: 49
Enabling self-reconfiguration on a video processing platform 在视频处理平台上启用自重构
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577676
K. F. Ackermann, Burghard Hoffmann, L. Indrusiak, M. Glesner
FPGA implementations of complex image processing algorithms are often limited in flexibility and by the amount of available chip resources. This article presents a hardware design of an adaptive self-reconfigurable video processing platform. Dynamic self-reconfiguration increases a designpsilas flexibility and enables the use of FPGAs with a fraction of resources actually needed by the algorithm. As a case study two implementation approaches of a complex frame-grabber with a set of dynamically reconfigurable kernels are evaluated and further improvements are outlined.
复杂图像处理算法的FPGA实现通常受到灵活性和可用芯片资源数量的限制。本文介绍了一种自适应自重构视频处理平台的硬件设计。动态自重构增加了设计的灵活性,并使fpga的使用与算法实际需要的资源的一小部分。作为一个案例研究,评估了具有一组动态可重构内核的复杂帧捕获器的两种实现方法,并概述了进一步的改进。
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引用次数: 8
The effect of real-time software reuse in FPGAs and microcontrollers with respect to software faults fpga和微控制器中软件实时复用对软件故障的影响
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577692
F. Salewski, S. Kowalewski
Reuse is considered as an important aspect in software design, but certain challenges have to be met if software reuse is applied in embedded systems. In these systems, specific requirements, as for example safety or real-time requirements, have to be considered, which typically complicate the reuse of software. Moreover, a large variety of hardware platforms is present in embedded systems. Those hardware platforms have different properties, which might affect the reuse of the corresponding software. In this paper, the different impacts of microcontrollers and FPGAs on software reuse are considered by empirical investigations. In particular, the investigations focus on the effect of this reuse on faults in real-time software. As a result, different benefits and drawbacks of software reuse were identified for microcontrollers and FPGAs.
重用被认为是软件设计的一个重要方面,但在嵌入式系统中应用软件重用必须面临一些挑战。在这些系统中,必须考虑特定的需求,例如安全性或实时需求,这通常会使软件的重用复杂化。此外,嵌入式系统中存在各种各样的硬件平台。这些硬件平台具有不同的属性,这可能会影响相应软件的重用。本文通过实证研究考虑了微控制器和fpga对软件重用的不同影响。特别是,研究的重点是这种重用对实时软件故障的影响。因此,对微控制器和fpga确定了软件重用的不同优点和缺点。
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引用次数: 1
TPR: Dead end aware table less position based routing scheme for low power data-centric wireless sensor networks
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577693
S. Madani, D. Weber, S. Mahlknecht
In this paper we present a Table less Position based Routing (TPR) scheme for low power data centric wireless sensor networks. TPR is localized, uses greedy forwarding approach, and does not rely on neighborhood information. These characteristics reduce the communication overhead (no neighborhood information exchange), make the protocol highly scalable (no routing tables are maintained and beacons are not exchanged when a node leaves or enters the networks), and it performs better in mobile environments (as the next hop is non-deterministic and is computed at real time). It also deals with dead end problems by a recovery strategy in a distributed and localized way. TPR is implemented in the OMNET++ based discrete event simulation environment PAWiS (simulation framework for low power wireless sensor networks). The results show that TPR provides guaranteed delivery, extended network life time, and a mechanism to route on the basis of end to end delay and/or energy consumption.
本文提出了一种用于低功耗数据中心无线传感器网络的无表位置路由(TPR)方案。TPR是局部化的,采用贪婪转发方法,不依赖邻域信息。这些特征减少了通信开销(没有邻居信息交换),使协议具有高度可扩展性(当节点离开或进入网络时不维护路由表和不交换信标),并且在移动环境中性能更好(因为下一跳是不确定的,并且是实时计算的)。它还通过分布式和本地化的恢复策略处理死胡同问题。TPR是在基于omnet++的离散事件仿真环境PAWiS(低功耗无线传感器网络仿真框架)中实现的。结果表明,TPR提供了保证交付、延长网络寿命和基于端到端延迟和/或能量消耗的路由机制。
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引用次数: 6
Services discovery and composition in Intelligent Environments for mobile devices 移动设备智能环境中的服务发现和组合
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577711
Reiner F. Perozzo, C. Pereira
Since the latest years, residential automation has been becoming a very discussed and recurrent subject. Part of such success is given by the meaningful diffusion and offer of portable electronic devices, with great power of computation, low energy consumption and, mainly, high level of connectivity. Joining the residential automation, the term ldquointelligent environmentsrdquo (IE) has been being defined, which brings a paradigm change, not considering the fact of just controlling devices, and leaving for a world where these are aware of everything that surrounds them. This paper proposes an architecture on management of services in IE for mobile devices, such as PDAs, cell phones and smart phones. The proposed architecture has three main characteristics: (i) discovery and remote composition of available services in the IE; (ii) adaptation of services and functionalities according to the userpsilas profile, using security policies with different levels of accessing the system; (iii) flexibility in the insertion of new residential automation devices, adding, dynamically, services to the IE. The architecture validation is presented through a case study which utilizes as scenery an automated seminaries room.
近年来,住宅自动化已成为一个经常讨论和反复出现的主题。这种成功的部分原因是便携式电子设备的有意义的普及和提供,这些设备具有强大的计算能力,低能耗,主要是高水平的连接。加入住宅自动化,“智能环境”(IE)一词已经被定义,它带来了范式的变化,不再考虑仅仅控制设备的事实,而是进入一个能够感知周围一切的世界。本文提出了一种用于pda、手机和智能手机等移动设备的IE服务管理体系结构。提出的体系结构有三个主要特点:(i) IE中可用服务的发现和远程组合;(ii)根据用户的个人资料调整服务和功能,采用不同访问系统级别的安全策略;(iii)灵活地插入新的住宅自动化设备,动态地为IE增加服务。架构验证是通过一个案例研究来展示的,该案例研究利用了一个自动化的神学院房间作为场景。
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引用次数: 1
Infrastructure for web-based administration of embedded systems 用于基于web的嵌入式系统管理的基础设施
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577682
C. Hochberger, Christian Meusel
Today, many embedded systems are equipped with network interfaces. Thus, web based management and administration are often required in such embedded systems. General approaches, which are widely available, fail to work on those resource constrained devices. Yet, there exists a necessity to support rapid development for dynamically generated pages. In this contribution we present a framework that will be usable on many embedded systems and also helps the web developer to simplify the document structure.
今天,许多嵌入式系统都配备了网络接口。因此,在这样的嵌入式系统中经常需要基于web的管理和管理。广泛使用的一般方法无法在这些资源受限的设备上工作。但是,有必要支持动态生成页面的快速开发。在这篇文章中,我们提出了一个框架,可以在许多嵌入式系统上使用,也可以帮助web开发人员简化文档结构。
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引用次数: 0
A digital receiver architecture for RFID readers RFID阅读器的数字接收器架构
Pub Date : 2008-06-11 DOI: 10.1109/SIES.2008.4577685
C. Angerer
This paper presents a digital receiver architecture for an RFID reader. The main challenge in RFID reader design is the detection of the backscattered signals from the tags, which can be severely complicated due to the largely varying scale of possible receive powers. Furthermore noise, which power depends on the environment can degrade the detection performance. The detection of the signals of the tags is additionally impeded by the very strong self interference at the reader with the carrier it needs to send in order to supply the tags with energy. To fight these various disturbances, a new RFID receiver algorithm is proposed, that sets its decision threshold adaptively, depending on the strength of the input signal, the noise power at the receiver and the extent of the carrier interference. This is the first algorithm for signal detection in RFID, setting its threshold accordingly to the environmental conditions, and thus leading to near optimum performance. Details of the implementation of the digital receiver architecture on an FPGA are introduced. Bit error ratio measurements have been carried out to rate the receivers performance, which have never been shown before for RFID receivers. Presented measurement results substantiate the performance of the suggested algorithm.
本文提出了一种RFID阅读器的数字接收机结构。RFID阅读器设计的主要挑战是检测来自标签的反向散射信号,由于可能的接收功率的很大程度上变化,这可能非常复杂。此外,噪声会降低检测性能,其功率取决于环境。另外,标签信号的检测受到读取器与它需要发送的载体的非常强的自干扰的阻碍,以便为标签提供能量。为了对抗这些干扰,提出了一种新的RFID接收机算法,该算法根据输入信号的强度、接收机处的噪声功率和载波干扰的程度自适应地设置其决策阈值。这是RFID中第一个用于信号检测的算法,根据环境条件设置其阈值,从而导致接近最佳性能。介绍了数字接收机结构在FPGA上的具体实现。误码率测量已被用于评估接收器的性能,这在RFID接收器中从未出现过。给出的测量结果证实了所提算法的性能。
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引用次数: 28
期刊
2008 International Symposium on Industrial Embedded Systems
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