Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577677
Kenji Funaoka, Akira Takeda, S. Kato, N. Yamasaki
Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulability improvement but also energy efficiency for the systems. In this paper, real-time dynamic voltage and frequency scaling (RT DVFS) techniques based on the theoretically optimal real-time static voltage and frequency scaling (RTSVFS) techniques proposed in our previous work are presented for multiprocessor systems. Simulation results show that RT-DVFS covers up the disadvantages of RT-SVFS in the sense that RTDVFS are not practically affected by the difference among systems, whereas the energy consumption of RT-SVFS highly depends on the selectable processor frequency especially in high system utilization.
{"title":"Dynamic voltage and frequency scaling for optimal real-time scheduling on multiprocessors","authors":"Kenji Funaoka, Akira Takeda, S. Kato, N. Yamasaki","doi":"10.1109/SIES.2008.4577677","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577677","url":null,"abstract":"Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulability improvement but also energy efficiency for the systems. In this paper, real-time dynamic voltage and frequency scaling (RT DVFS) techniques based on the theoretically optimal real-time static voltage and frequency scaling (RTSVFS) techniques proposed in our previous work are presented for multiprocessor systems. Simulation results show that RT-DVFS covers up the disadvantages of RT-SVFS in the sense that RTDVFS are not practically affected by the difference among systems, whereas the energy consumption of RT-SVFS highly depends on the selectable processor frequency especially in high system utilization.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125123780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577684
Hankook Jang, Sang-Hwa Chung, Dae-Hyun Yoo
We develop a hybrid TCP/IP offload engine (hybrid TOE) that processes TCP/IP via hardware/software coprocessing based on an FPGA and a general-purpose embedded processor. We also develop an efficient remote direct memory access (RDMA) mechanism that is tightly coupled with the hybrid TOE. In this mechanism, the hybrid TOE performs CRC calculations using hardware modules and supports zero-copy data transmission; the host CPU simply generates and processes RDMA protocol headers. By using the hybrid TOE and the RDMA mechanism, computer systems can achieve good network performance with very low CPU utilizations, and thus they can be expected to show a great improvement in overall performance. In experiments on a gigabit Ethernet network, although the embedded processor operated with a 300 MHz core clock, which was one-seventh the speed of the host CPUpsilas clock, the hybrid TOE showed a minimum latency of 17.4 mus and a maximum bandwidth of 736 Mbps. The RDMA mechanism exhibited a minimum latency of 20.6 mus and a maximum bandwidth of 642 Mbps. Most importantly, the hybrid TOE and the TOE-based RDMA mechanism gave CPU utilizations of less than 5.6% and 8.4%, respectively-approximately one-tenth the utilizations when TCP/IP and TCP/IP-based RDMA were processed by the host CPU.
{"title":"Implementation of an efficient RDMA mechanism tightly coupled with a TCP/IP offload engine","authors":"Hankook Jang, Sang-Hwa Chung, Dae-Hyun Yoo","doi":"10.1109/SIES.2008.4577684","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577684","url":null,"abstract":"We develop a hybrid TCP/IP offload engine (hybrid TOE) that processes TCP/IP via hardware/software coprocessing based on an FPGA and a general-purpose embedded processor. We also develop an efficient remote direct memory access (RDMA) mechanism that is tightly coupled with the hybrid TOE. In this mechanism, the hybrid TOE performs CRC calculations using hardware modules and supports zero-copy data transmission; the host CPU simply generates and processes RDMA protocol headers. By using the hybrid TOE and the RDMA mechanism, computer systems can achieve good network performance with very low CPU utilizations, and thus they can be expected to show a great improvement in overall performance. In experiments on a gigabit Ethernet network, although the embedded processor operated with a 300 MHz core clock, which was one-seventh the speed of the host CPUpsilas clock, the hybrid TOE showed a minimum latency of 17.4 mus and a maximum bandwidth of 736 Mbps. The RDMA mechanism exhibited a minimum latency of 20.6 mus and a maximum bandwidth of 642 Mbps. Most importantly, the hybrid TOE and the TOE-based RDMA mechanism gave CPU utilizations of less than 5.6% and 8.4%, respectively-approximately one-tenth the utilizations when TCP/IP and TCP/IP-based RDMA were processed by the host CPU.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125789593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577689
Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes
Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.
{"title":"Validation of executable application models mapped onto network-on-chip platforms","authors":"Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, J. Nurmi, M. Glesner, F. Moraes","doi":"10.1109/SIES.2008.4577689","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577689","url":null,"abstract":"Due to the increasing design size, complexity, and heterogeneity of todaypsilas embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous models of computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor network-on-chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124541990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577715
Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, L. Thiele
SystemC becomes popular as an efficient system-level modelling language and simulation platform. However, the sole-thread simulation kernel obstacles its performance progress from the potential of modern multi-core machines. This is further aggravated by modern embedded applications that are getting more complex. In this paper, we propose a technique which supports the geographical distribution of an arbitrary number of SystemC simulations, without modifying the SystemC simulation kernel. This technique is suited to distribute functional and approximated-timed TLM simulation. We integrate this technique into a complete MPSoC design space exploration framework and the improvement gained is promising.
{"title":"Scalably distributed SystemC simulation for embedded applications","authors":"Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, L. Thiele","doi":"10.1109/SIES.2008.4577715","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577715","url":null,"abstract":"SystemC becomes popular as an efficient system-level modelling language and simulation platform. However, the sole-thread simulation kernel obstacles its performance progress from the potential of modern multi-core machines. This is further aggravated by modern embedded applications that are getting more complex. In this paper, we propose a technique which supports the geographical distribution of an arbitrary number of SystemC simulations, without modifying the SystemC simulation kernel. This technique is suited to distribute functional and approximated-timed TLM simulation. We integrate this technique into a complete MPSoC design space exploration framework and the improvement gained is promising.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126226753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577676
K. F. Ackermann, Burghard Hoffmann, L. Indrusiak, M. Glesner
FPGA implementations of complex image processing algorithms are often limited in flexibility and by the amount of available chip resources. This article presents a hardware design of an adaptive self-reconfigurable video processing platform. Dynamic self-reconfiguration increases a designpsilas flexibility and enables the use of FPGAs with a fraction of resources actually needed by the algorithm. As a case study two implementation approaches of a complex frame-grabber with a set of dynamically reconfigurable kernels are evaluated and further improvements are outlined.
{"title":"Enabling self-reconfiguration on a video processing platform","authors":"K. F. Ackermann, Burghard Hoffmann, L. Indrusiak, M. Glesner","doi":"10.1109/SIES.2008.4577676","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577676","url":null,"abstract":"FPGA implementations of complex image processing algorithms are often limited in flexibility and by the amount of available chip resources. This article presents a hardware design of an adaptive self-reconfigurable video processing platform. Dynamic self-reconfiguration increases a designpsilas flexibility and enables the use of FPGAs with a fraction of resources actually needed by the algorithm. As a case study two implementation approaches of a complex frame-grabber with a set of dynamically reconfigurable kernels are evaluated and further improvements are outlined.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"151 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124197899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577692
F. Salewski, S. Kowalewski
Reuse is considered as an important aspect in software design, but certain challenges have to be met if software reuse is applied in embedded systems. In these systems, specific requirements, as for example safety or real-time requirements, have to be considered, which typically complicate the reuse of software. Moreover, a large variety of hardware platforms is present in embedded systems. Those hardware platforms have different properties, which might affect the reuse of the corresponding software. In this paper, the different impacts of microcontrollers and FPGAs on software reuse are considered by empirical investigations. In particular, the investigations focus on the effect of this reuse on faults in real-time software. As a result, different benefits and drawbacks of software reuse were identified for microcontrollers and FPGAs.
{"title":"The effect of real-time software reuse in FPGAs and microcontrollers with respect to software faults","authors":"F. Salewski, S. Kowalewski","doi":"10.1109/SIES.2008.4577692","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577692","url":null,"abstract":"Reuse is considered as an important aspect in software design, but certain challenges have to be met if software reuse is applied in embedded systems. In these systems, specific requirements, as for example safety or real-time requirements, have to be considered, which typically complicate the reuse of software. Moreover, a large variety of hardware platforms is present in embedded systems. Those hardware platforms have different properties, which might affect the reuse of the corresponding software. In this paper, the different impacts of microcontrollers and FPGAs on software reuse are considered by empirical investigations. In particular, the investigations focus on the effect of this reuse on faults in real-time software. As a result, different benefits and drawbacks of software reuse were identified for microcontrollers and FPGAs.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"7 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125657227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577693
S. Madani, D. Weber, S. Mahlknecht
In this paper we present a Table less Position based Routing (TPR) scheme for low power data centric wireless sensor networks. TPR is localized, uses greedy forwarding approach, and does not rely on neighborhood information. These characteristics reduce the communication overhead (no neighborhood information exchange), make the protocol highly scalable (no routing tables are maintained and beacons are not exchanged when a node leaves or enters the networks), and it performs better in mobile environments (as the next hop is non-deterministic and is computed at real time). It also deals with dead end problems by a recovery strategy in a distributed and localized way. TPR is implemented in the OMNET++ based discrete event simulation environment PAWiS (simulation framework for low power wireless sensor networks). The results show that TPR provides guaranteed delivery, extended network life time, and a mechanism to route on the basis of end to end delay and/or energy consumption.
{"title":"TPR: Dead end aware table less position based routing scheme for low power data-centric wireless sensor networks","authors":"S. Madani, D. Weber, S. Mahlknecht","doi":"10.1109/SIES.2008.4577693","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577693","url":null,"abstract":"In this paper we present a Table less Position based Routing (TPR) scheme for low power data centric wireless sensor networks. TPR is localized, uses greedy forwarding approach, and does not rely on neighborhood information. These characteristics reduce the communication overhead (no neighborhood information exchange), make the protocol highly scalable (no routing tables are maintained and beacons are not exchanged when a node leaves or enters the networks), and it performs better in mobile environments (as the next hop is non-deterministic and is computed at real time). It also deals with dead end problems by a recovery strategy in a distributed and localized way. TPR is implemented in the OMNET++ based discrete event simulation environment PAWiS (simulation framework for low power wireless sensor networks). The results show that TPR provides guaranteed delivery, extended network life time, and a mechanism to route on the basis of end to end delay and/or energy consumption.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121401311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577711
Reiner F. Perozzo, C. Pereira
Since the latest years, residential automation has been becoming a very discussed and recurrent subject. Part of such success is given by the meaningful diffusion and offer of portable electronic devices, with great power of computation, low energy consumption and, mainly, high level of connectivity. Joining the residential automation, the term ldquointelligent environmentsrdquo (IE) has been being defined, which brings a paradigm change, not considering the fact of just controlling devices, and leaving for a world where these are aware of everything that surrounds them. This paper proposes an architecture on management of services in IE for mobile devices, such as PDAs, cell phones and smart phones. The proposed architecture has three main characteristics: (i) discovery and remote composition of available services in the IE; (ii) adaptation of services and functionalities according to the userpsilas profile, using security policies with different levels of accessing the system; (iii) flexibility in the insertion of new residential automation devices, adding, dynamically, services to the IE. The architecture validation is presented through a case study which utilizes as scenery an automated seminaries room.
{"title":"Services discovery and composition in Intelligent Environments for mobile devices","authors":"Reiner F. Perozzo, C. Pereira","doi":"10.1109/SIES.2008.4577711","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577711","url":null,"abstract":"Since the latest years, residential automation has been becoming a very discussed and recurrent subject. Part of such success is given by the meaningful diffusion and offer of portable electronic devices, with great power of computation, low energy consumption and, mainly, high level of connectivity. Joining the residential automation, the term ldquointelligent environmentsrdquo (IE) has been being defined, which brings a paradigm change, not considering the fact of just controlling devices, and leaving for a world where these are aware of everything that surrounds them. This paper proposes an architecture on management of services in IE for mobile devices, such as PDAs, cell phones and smart phones. The proposed architecture has three main characteristics: (i) discovery and remote composition of available services in the IE; (ii) adaptation of services and functionalities according to the userpsilas profile, using security policies with different levels of accessing the system; (iii) flexibility in the insertion of new residential automation devices, adding, dynamically, services to the IE. The architecture validation is presented through a case study which utilizes as scenery an automated seminaries room.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130352099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577706
Marta Beltrán, A. Guzmán
New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. There are a lot of multiprocessor systems implemented on FPGApsilas but they are very often application and platform specific. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design is application and platform independent and furthermore, two different memory models, shared or distributed memory, can be used depending on the designer requirements. Therefore it is not only a multiprocessor on chip, it can be a multicomputer on chip too.
{"title":"Designing HIPAOC: High Performance Architecture On Chip","authors":"Marta Beltrán, A. Guzmán","doi":"10.1109/SIES.2008.4577706","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577706","url":null,"abstract":"New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. There are a lot of multiprocessor systems implemented on FPGApsilas but they are very often application and platform specific. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design is application and platform independent and furthermore, two different memory models, shared or distributed memory, can be used depending on the designer requirements. Therefore it is not only a multiprocessor on chip, it can be a multicomputer on chip too.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124418894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-06-11DOI: 10.1109/SIES.2008.4577688
J. Metrôlho, C. Couto, Carlos Alberto Silva, A. Tavares
This paper presents a novel architecture description language, MiADL. This language is capable of specifying a wide class of ISAs by exploring the common features found in instructions, obtaining compact descriptions. Descriptionpsilas efficiency and expressiveness is demonstrated with examples that compare MiADL with other related works, using complex ISAs of contemporary processors. The semantics of new constructs of the language is also presented. These permit smaller descriptions over other ADLs. Results achieved with simulators generated from this language revealed a speed-up over other contributions. A comparison in terms of description effectiveness and simulator performance is presented.
{"title":"A language for automatic generation of fast instruction-set compiled simulators","authors":"J. Metrôlho, C. Couto, Carlos Alberto Silva, A. Tavares","doi":"10.1109/SIES.2008.4577688","DOIUrl":"https://doi.org/10.1109/SIES.2008.4577688","url":null,"abstract":"This paper presents a novel architecture description language, MiADL. This language is capable of specifying a wide class of ISAs by exploring the common features found in instructions, obtaining compact descriptions. Descriptionpsilas efficiency and expressiveness is demonstrated with examples that compare MiADL with other related works, using complex ISAs of contemporary processors. The semantics of new constructs of the language is also presented. These permit smaller descriptions over other ADLs. Results achieved with simulators generated from this language revealed a speed-up over other contributions. A comparison in terms of description effectiveness and simulator performance is presented.","PeriodicalId":438401,"journal":{"name":"2008 International Symposium on Industrial Embedded Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132559620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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